1* USB2 ChipIdea USB controller for ci13xxx
2
3Required properties:
4- compatible: should be one of:
5	"fsl,imx23-usb"
6	"fsl,imx27-usb"
7	"fsl,imx28-usb"
8	"fsl,imx6q-usb"
9	"fsl,imx6sl-usb"
10	"fsl,imx6sx-usb"
11	"fsl,imx6ul-usb"
12	"fsl,imx7d-usb"
13	"lsi,zevio-usb"
14	"qcom,ci-hdrc"
15	"chipidea,usb2"
16	"xlnx,zynq-usb-2.20a"
17- reg: base address and length of the registers
18- interrupts: interrupt for the USB controller
19
20Recommended properies:
21- phy_type: the type of the phy connected to the core. Should be one
22  of "utmi", "utmi_wide", "ulpi", "serial" or "hsic". Without this
23  property the PORTSC register won't be touched.
24- dr_mode: One of "host", "peripheral" or "otg". Defaults to "otg"
25
26Deprecated properties:
27- usb-phy:      phandle for the PHY device. Use "phys" instead.
28- fsl,usbphy: phandle of usb phy that connects to the port. Use "phys" instead.
29
30Optional properties:
31- clocks: reference to the USB clock
32- phys: reference to the USB PHY
33- phy-names: should be "usb-phy"
34- vbus-supply: reference to the VBUS regulator
35- maximum-speed: limit the maximum connection speed to "full-speed".
36- tpl-support: TPL (Targeted Peripheral List) feature for targeted hosts
37- itc-setting: interrupt threshold control register control, the setting
38  should be aligned with ITC bits at register USBCMD.
39- ahb-burst-config: it is vendor dependent, the required value should be
40  aligned with AHBBRST at SBUSCFG, the range is from 0x0 to 0x7. This
41  property is used to change AHB burst configuration, check the chipidea
42  spec for meaning of each value. If this property is not existed, it
43  will use the reset value.
44- tx-burst-size-dword: it is vendor dependent, the tx burst size in dword
45  (4 bytes), This register represents the maximum length of a the burst
46  in 32-bit words while moving data from system memory to the USB
47  bus, the value of this property will only take effect if property
48  "ahb-burst-config" is set to 0, if this property is missing the reset
49  default of the hardware implementation will be used.
50- rx-burst-size-dword: it is vendor dependent, the rx burst size in dword
51  (4 bytes), This register represents the maximum length of a the burst
52  in 32-bit words while moving data from the USB bus to system memory,
53  the value of this property will only take effect if property
54  "ahb-burst-config" is set to 0, if this property is missing the reset
55  default of the hardware implementation will be used.
56- extcon: phandles to external connector devices. First phandle should point to
57  external connector, which provide "USB" cable events, the second should point
58  to external connector device, which provide "USB-HOST" cable events. If one
59  of the external connector devices is not required, empty <0> phandle should
60  be specified.
61- phy-clkgate-delay-us: the delay time (us) between putting the PHY into
62  low power mode and gating the PHY clock.
63- non-zero-ttctrl-ttha: after setting this property, the value of register
64  ttctrl.ttha will be 0x7f; if not, the value will be 0x0, this is the default
65  value. It needs to be very carefully for setting this property, it is
66  recommended that consult with your IC engineer before setting this value.
67  On the most of chipidea platforms, the "usage_tt" flag at RTL is 0, so this
68  property only affects siTD.
69  If this property is not set, the max packet size is 1023 bytes, and if
70  the total of packet size for pervious transactions are more than 256 bytes,
71  it can't accept any transactions within this frame. The use case is single
72  transaction, but higher frame rate.
73  If this property is set, the max packet size is 188 bytes, it can handle
74  more transactions than above case, it can accept transactions until it
75  considers the left room size within frame is less than 188 bytes, software
76  needs to make sure it does not send more than 90%
77  maximum_periodic_data_per_frame. The use case is multiple transactions, but
78  less frame rate.
79- mux-controls: The mux control for toggling host/device output of this
80  controller. It's expected that a mux state of 0 indicates device mode and a
81  mux state of 1 indicates host mode.
82- mux-control-names: Shall be "usb_switch" if mux-controls is specified.
83
84i.mx specific properties
85- fsl,usbmisc: phandler of non-core register device, with one
86  argument that indicate usb controller index
87- disable-over-current: disable over current detect
88- over-current-active-high: over current signal polarity is high active,
89  typically over current signal polarity is low active.
90- external-vbus-divider: enables off-chip resistor divider for Vbus
91
92Example:
93
94	usb@f7ed0000 {
95		compatible = "chipidea,usb2";
96		reg = <0xf7ed0000 0x10000>;
97		interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
98		clocks = <&chip CLKID_USB0>;
99		phys = <&usb_phy0>;
100		phy-names = "usb-phy";
101		vbus-supply = <&reg_usb0_vbus>;
102		itc-setting = <0x4>; /* 4 micro-frames */
103		 /* Incremental burst of unspecified length */
104		ahb-burst-config = <0x0>;
105		tx-burst-size-dword = <0x10>; /* 64 bytes */
106		rx-burst-size-dword = <0x10>;
107		extcon = <0>, <&usb_id>;
108		phy-clkgate-delay-us = <400>;
109		mux-controls = <&usb_switch>;
110		mux-control-names = "usb_switch";
111	};
112