1* Universal Flash Storage (UFS) Host Controller
2
3UFSHC nodes are defined to describe on-chip UFS host controllers.
4Each UFS controller instance should have its own node.
5
6Required properties:
7- compatible		: must contain "jedec,ufs-1.1" or "jedec,ufs-2.0", may
8			  also list one or more of the following:
9					  "qcom,msm8994-ufshc"
10					  "qcom,msm8996-ufshc"
11					  "qcom,ufshc"
12- interrupts        : <interrupt mapping for UFS host controller IRQ>
13- reg               : <registers mapping>
14
15Optional properties:
16- phys                  : phandle to UFS PHY node
17- phy-names             : the string "ufsphy" when is found in a node, along
18                          with "phys" attribute, provides phandle to UFS PHY node
19- vdd-hba-supply        : phandle to UFS host controller supply regulator node
20- vcc-supply            : phandle to VCC supply regulator node
21- vccq-supply           : phandle to VCCQ supply regulator node
22- vccq2-supply          : phandle to VCCQ2 supply regulator node
23- vcc-supply-1p8        : For embedded UFS devices, valid VCC range is 1.7-1.95V
24                          or 2.7-3.6V. This boolean property when set, specifies
25			  to use low voltage range of 1.7-1.95V. Note for external
26			  UFS cards this property is invalid and valid VCC range is
27			  always 2.7-3.6V.
28- vcc-max-microamp      : specifies max. load that can be drawn from vcc supply
29- vccq-max-microamp     : specifies max. load that can be drawn from vccq supply
30- vccq2-max-microamp    : specifies max. load that can be drawn from vccq2 supply
31- <name>-fixed-regulator : boolean property specifying that <name>-supply is a fixed regulator
32
33- clocks                : List of phandle and clock specifier pairs
34- clock-names           : List of clock input name strings sorted in the same
35                          order as the clocks property.
36- freq-table-hz		: Array of <min max> operating frequencies stored in the same
37                          order as the clocks property. If this property is not
38			  defined or a value in the array is "0" then it is assumed
39			  that the frequency is set by the parent clock or a
40			  fixed rate clock source.
41-lanes-per-direction	: number of lanes available per direction - either 1 or 2.
42			  Note that it is assume same number of lanes is used both
43			  directions at once. If not specified, default is 2 lanes per direction.
44- resets            : reset node register
45- reset-names       : describe reset node register, the "rst" corresponds to reset the whole UFS IP.
46
47Note: If above properties are not defined it can be assumed that the supply
48regulators or clocks are always on.
49
50Example:
51	ufshc@fc598000 {
52		compatible = "jedec,ufs-1.1";
53		reg = <0xfc598000 0x800>;
54		interrupts = <0 28 0>;
55
56		vdd-hba-supply = <&xxx_reg0>;
57		vdd-hba-fixed-regulator;
58		vcc-supply = <&xxx_reg1>;
59		vcc-supply-1p8;
60		vccq-supply = <&xxx_reg2>;
61		vccq2-supply = <&xxx_reg3>;
62		vcc-max-microamp = 500000;
63		vccq-max-microamp = 200000;
64		vccq2-max-microamp = 200000;
65
66		clocks = <&core 0>, <&ref 0>, <&phy 0>, <&iface 0>;
67		clock-names = "core_clk", "ref_clk", "phy_clk", "iface_clk";
68		freq-table-hz = <100000000 200000000>, <0 0>, <0 0>, <0 0>;
69		resets = <&reset 0 1>;
70		reset-names = "rst";
71		phys = <&ufsphy1>;
72		phy-names = "ufsphy";
73	};
74