1* Hisilicon Universal Flash Storage (UFS) Host Controller
2
3UFS nodes are defined to describe on-chip UFS hardware macro.
4Each UFS Host Controller should have its own node.
5
6Required properties:
7- compatible        : compatible list, contains one of the following -
8					"hisilicon,hi3660-ufs", "jedec,ufs-1.1" for hisi ufs
9					host controller present on Hi36xx chipset.
10- reg               : should contain UFS register address space & UFS SYS CTRL register address,
11- interrupt-parent  : interrupt device
12- interrupts        : interrupt number
13- clocks	        : List of phandle and clock specifier pairs
14- clock-names       : List of clock input name strings sorted in the same
15					order as the clocks property. "ref_clk", "phy_clk" is optional
16- freq-table-hz     : Array of <min max> operating frequencies stored in the same
17                      order as the clocks property. If this property is not
18                      defined or a value in the array is "0" then it is assumed
19                      that the frequency is set by the parent clock or a
20                      fixed rate clock source.
21- resets            : describe reset node register
22- reset-names       : reset node register, the "rst" corresponds to reset the whole UFS IP.
23
24Example:
25
26	ufs: ufs@ff3b0000 {
27		compatible = "hisilicon,hi3660-ufs", "jedec,ufs-1.1";
28		/* 0: HCI standard */
29		/* 1: UFS SYS CTRL */
30		reg = <0x0 0xff3b0000 0x0 0x1000>,
31			<0x0 0xff3b1000 0x0 0x1000>;
32		interrupt-parent = <&gic>;
33		interrupts = <GIC_SPI 278 IRQ_TYPE_LEVEL_HIGH>;
34		clocks = <&crg_ctrl HI3660_CLK_GATE_UFSIO_REF>,
35			<&crg_ctrl HI3660_CLK_GATE_UFSPHY_CFG>;
36		clock-names = "ref_clk", "phy_clk";
37		freq-table-hz = <0 0>, <0 0>;
38		/* offset: 0x84; bit: 12  */
39		resets = <&crg_rst 0x84 12>;
40		reset-names = "rst";
41	};
42