1Binding for MTK SPI controller
2
3Required properties:
4- compatible: should be one of the following.
5    - mediatek,mt2701-spi: for mt2701 platforms
6    - mediatek,mt2712-spi: for mt2712 platforms
7    - mediatek,mt6589-spi: for mt6589 platforms
8    - mediatek,mt7622-spi: for mt7622 platforms
9    - mediatek,mt8135-spi: for mt8135 platforms
10    - mediatek,mt8173-spi: for mt8173 platforms
11
12- #address-cells: should be 1.
13
14- #size-cells: should be 0.
15
16- reg: Address and length of the register set for the device
17
18- interrupts: Should contain spi interrupt
19
20- clocks: phandles to input clocks.
21  The first should be one of the following. It's PLL.
22   -  <&clk26m>: specify parent clock 26MHZ.
23   -  <&topckgen CLK_TOP_SYSPLL3_D2>: specify parent clock 109MHZ.
24				      It's the default one.
25   -  <&topckgen CLK_TOP_SYSPLL4_D2>: specify parent clock 78MHZ.
26   -  <&topckgen CLK_TOP_UNIVPLL2_D4>: specify parent clock 104MHZ.
27   -  <&topckgen CLK_TOP_UNIVPLL1_D8>: specify parent clock 78MHZ.
28  The second should be <&topckgen CLK_TOP_SPI_SEL>. It's clock mux.
29  The third is <&pericfg CLK_PERI_SPI0>. It's clock gate.
30
31- clock-names: shall be "parent-clk" for the parent clock, "sel-clk" for the
32  muxes clock, and "spi-clk" for the clock gate.
33
34Optional properties:
35-cs-gpios: see spi-bus.txt.
36
37- mediatek,pad-select: specify which pins group(ck/mi/mo/cs) spi
38  controller used. This is an array, the element value should be 0~3,
39  only required for MT8173.
40    0: specify GPIO69,70,71,72 for spi pins.
41    1: specify GPIO102,103,104,105 for spi pins.
42    2: specify GPIO128,129,130,131 for spi pins.
43    3: specify GPIO5,6,7,8 for spi pins.
44
45Example:
46
47- SoC Specific Portion:
48spi: spi@1100a000 {
49	compatible = "mediatek,mt8173-spi";
50	#address-cells = <1>;
51	#size-cells = <0>;
52	reg = <0 0x1100a000 0 0x1000>;
53	interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_LOW>;
54	clocks = <&topckgen CLK_TOP_SYSPLL3_D2>,
55		 <&topckgen CLK_TOP_SPI_SEL>,
56		 <&pericfg CLK_PERI_SPI0>;
57	clock-names = "parent-clk", "sel-clk", "spi-clk";
58	cs-gpios = <&pio 105 GPIO_ACTIVE_LOW>, <&pio 72 GPIO_ACTIVE_LOW>;
59	mediatek,pad-select = <1>, <0>;
60};
61