1Qualcomm Technologies, Inc. GENI Serial Engine QUP Wrapper Controller
2
3Generic Interface (GENI) based Qualcomm Universal Peripheral (QUP) wrapper
4is a programmable module for supporting a wide range of serial interfaces
5like UART, SPI, I2C, I3C, etc. A single QUP module can provide upto 8 Serial
6Interfaces, using its internal Serial Engines. The GENI Serial Engine QUP
7Wrapper controller is modeled as a node with zero or more child nodes each
8representing a serial engine.
9
10Required properties:
11- compatible:		Must be "qcom,geni-se-qup".
12- reg:			Must contain QUP register address and length.
13- clock-names:		Must contain "m-ahb" and "s-ahb".
14- clocks:		AHB clocks needed by the device.
15
16Required properties if child node exists:
17- #address-cells: 	Must be <1> for Serial Engine Address
18- #size-cells: 		Must be <1> for Serial Engine Address Size
19- ranges: 		Must be present
20
21Properties for children:
22
23A GENI based QUP wrapper controller node can contain 0 or more child nodes
24representing serial devices.  These serial devices can be a QCOM UART, I2C
25controller, SPI controller, or some combination of aforementioned devices.
26Please refer below the child node definitions for the supported serial
27interface protocols.
28
29Qualcomm Technologies Inc. GENI Serial Engine based I2C Controller
30
31Required properties:
32- compatible:		Must be "qcom,geni-i2c".
33- reg: 			Must contain QUP register address and length.
34- interrupts: 		Must contain I2C interrupt.
35- clock-names: 		Must contain "se".
36- clocks: 		Serial engine core clock needed by the device.
37- #address-cells:	Must be <1> for I2C device address.
38- #size-cells:		Must be <0> as I2C addresses have no size component.
39
40Optional property:
41- clock-frequency:	Desired I2C bus clock frequency in Hz.
42			When missing default to 100000Hz.
43
44Child nodes should conform to I2C bus binding as described in i2c.txt.
45
46Qualcomm Technologies Inc. GENI Serial Engine based UART Controller
47
48Required properties:
49- compatible:		Must be "qcom,geni-debug-uart" or "qcom,geni-uart".
50- reg: 			Must contain UART register location and length.
51- interrupts: 		Must contain UART core interrupts.
52- clock-names:		Must contain "se".
53- clocks:		Serial engine core clock needed by the device.
54
55Qualcomm Technologies Inc. GENI Serial Engine based SPI Controller
56
57Required properties:
58- compatible:		Must contain "qcom,geni-spi".
59- reg:			Must contain SPI register location and length.
60- interrupts:		Must contain SPI controller interrupts.
61- clock-names:		Must contain "se".
62- clocks:		Serial engine core clock needed by the device.
63- spi-max-frequency:	Specifies maximum SPI clock frequency, units - Hz.
64- #address-cells:	Must be <1> to define a chip select address on
65			the SPI bus.
66- #size-cells:		Must be <0>.
67
68SPI slave nodes must be children of the SPI master node and conform to SPI bus
69binding as described in Documentation/devicetree/bindings/spi/spi-bus.txt.
70
71Example:
72	geniqup@8c0000 {
73		compatible = "qcom,geni-se-qup";
74		reg = <0x8c0000 0x6000>;
75		clock-names = "m-ahb", "s-ahb";
76		clocks = <&clock_gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
77			<&clock_gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
78		#address-cells = <1>;
79		#size-cells = <1>;
80		ranges;
81
82		i2c0: i2c@a94000 {
83			compatible = "qcom,geni-i2c";
84			reg = <0xa94000 0x4000>;
85			interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
86			clock-names = "se";
87			clocks = <&clock_gcc GCC_QUPV3_WRAP0_S5_CLK>;
88			pinctrl-names = "default", "sleep";
89			pinctrl-0 = <&qup_1_i2c_5_active>;
90			pinctrl-1 = <&qup_1_i2c_5_sleep>;
91			#address-cells = <1>;
92			#size-cells = <0>;
93		};
94
95		uart0: serial@a88000 {
96			compatible = "qcom,geni-debug-uart";
97			reg = <0xa88000 0x7000>;
98			interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
99			clock-names = "se";
100			clocks = <&clock_gcc GCC_QUPV3_WRAP0_S0_CLK>;
101			pinctrl-names = "default", "sleep";
102			pinctrl-0 = <&qup_1_uart_3_active>;
103			pinctrl-1 = <&qup_1_uart_3_sleep>;
104		};
105
106		spi0: spi@a84000 {
107			compatible = "qcom,geni-spi";
108			reg = <0xa84000 0x4000>;
109			interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
110			clock-names = "se";
111			clocks = <&clock_gcc GCC_QUPV3_WRAP0_S0_CLK>;
112			pinctrl-names = "default", "sleep";
113			pinctrl-0 = <&qup_1_spi_2_active>;
114			pinctrl-1 = <&qup_1_spi_2_sleep>;
115			spi-max-frequency = <19200000>;
116			#address-cells = <1>;
117			#size-cells = <0>;
118		};
119	}
120