1* UART (Universal Asynchronous Receiver/Transmitter)
2
3Required properties:
4- compatible : one of:
5	- "ns8250"
6	- "ns16450"
7	- "ns16550a"
8	- "ns16550"
9	- "ns16750"
10	- "ns16850"
11	- For Tegra20, must contain "nvidia,tegra20-uart"
12	- For other Tegra, must contain '"nvidia,<chip>-uart",
13	  "nvidia,tegra20-uart"' where <chip> is tegra30, tegra114, tegra124,
14	  tegra132, or tegra210.
15	- "nxp,lpc3220-uart"
16	- "ralink,rt2880-uart"
17	- For MediaTek BTIF, must contain '"mediatek,<chip>-btif",
18	  "mediatek,mtk-btif"' where <chip> is mt7622, mt7623.
19	- "altr,16550-FIFO32"
20	- "altr,16550-FIFO64"
21	- "altr,16550-FIFO128"
22	- "fsl,16550-FIFO64"
23	- "fsl,ns16550"
24	- "ti,da830-uart"
25	- "aspeed,ast2400-vuart"
26	- "aspeed,ast2500-vuart"
27	- "nuvoton,npcm750-uart"
28	- "serial" if the port type is unknown.
29- reg : offset and length of the register set for the device.
30- interrupts : should contain uart interrupt.
31- clock-frequency : the input clock frequency for the UART
32	 or
33  clocks phandle to refer to the clk used as per Documentation/devicetree
34  /bindings/clock/clock-bindings.txt
35
36Optional properties:
37- current-speed : the current active speed of the UART.
38- reg-offset : offset to apply to the mapbase from the start of the registers.
39- reg-shift : quantity to shift the register offsets by.
40- reg-io-width : the size (in bytes) of the IO accesses that should be
41  performed on the device.  There are some systems that require 32-bit
42  accesses to the UART (e.g. TI davinci).
43- used-by-rtas : set to indicate that the port is in use by the OpenFirmware
44  RTAS and should not be registered.
45- no-loopback-test: set to indicate that the port does not implements loopback
46  test mode
47- fifo-size: the fifo size of the UART.
48- auto-flow-control: one way to enable automatic flow control support. The
49  driver is allowed to detect support for the capability even without this
50  property.
51- tx-threshold: Specify the TX FIFO low water indication for parts with
52  programmable TX FIFO thresholds.
53- resets : phandle + reset specifier pairs
54
55Note:
56* fsl,ns16550:
57  ------------
58  Freescale DUART is very similar to the PC16552D (and to a
59  pair of NS16550A), albeit with some nonstandard behavior such as
60  erratum A-004737 (relating to incorrect BRK handling).
61
62  Represents a single port that is compatible with the DUART found
63  on many Freescale chips (examples include mpc8349, mpc8548,
64  mpc8641d, p4080 and ls2085a).
65
66Example:
67
68	uart@80230000 {
69		compatible = "ns8250";
70		reg = <0x80230000 0x100>;
71		clock-frequency = <3686400>;
72		interrupts = <10>;
73		reg-shift = <2>;
74	};
75