1Qualcomm MSM8998 TLMM block
2
3This binding describes the Top Level Mode Multiplexer block found in the
4MSM8998 platform.
5
6- compatible:
7	Usage: required
8	Value type: <string>
9	Definition: must be "qcom,msm8998-pinctrl"
10
11- reg:
12	Usage: required
13	Value type: <prop-encoded-array>
14	Definition: the base address and size of the TLMM register space.
15
16- interrupts:
17	Usage: required
18	Value type: <prop-encoded-array>
19	Definition: should specify the TLMM summary IRQ.
20
21- interrupt-controller:
22	Usage: required
23	Value type: <none>
24	Definition: identifies this node as an interrupt controller
25
26- #interrupt-cells:
27	Usage: required
28	Value type: <u32>
29	Definition: must be 2. Specifying the pin number and flags, as defined
30		    in <dt-bindings/interrupt-controller/irq.h>
31
32- gpio-controller:
33	Usage: required
34	Value type: <none>
35	Definition: identifies this node as a gpio controller
36
37- #gpio-cells:
38	Usage: required
39	Value type: <u32>
40	Definition: must be 2. Specifying the pin number and flags, as defined
41		    in <dt-bindings/gpio/gpio.h>
42
43Please refer to ../gpio/gpio.txt and ../interrupt-controller/interrupts.txt for
44a general description of GPIO and interrupt bindings.
45
46Please refer to pinctrl-bindings.txt in this directory for details of the
47common pinctrl bindings used by client devices, including the meaning of the
48phrase "pin configuration node".
49
50The pin configuration nodes act as a container for an arbitrary number of
51subnodes. Each of these subnodes represents some desired configuration for a
52pin, a group, or a list of pins or groups. This configuration can include the
53mux function to select on those pin(s)/group(s), and various pin configuration
54parameters, such as pull-up, drive strength, etc.
55
56
57PIN CONFIGURATION NODES:
58
59The name of each subnode is not important; all subnodes should be enumerated
60and processed purely based on their content.
61
62Each subnode only affects those parameters that are explicitly listed. In
63other words, a subnode that lists a mux function but no pin configuration
64parameters implies no information about any pin configuration parameters.
65Similarly, a pin subnode that describes a pullup parameter implies no
66information about e.g. the mux function.
67
68
69The following generic properties as defined in pinctrl-bindings.txt are valid
70to specify in a pin configuration subnode:
71
72- pins:
73	Usage: required
74	Value type: <string-array>
75	Definition: List of gpio pins affected by the properties specified in
76		    this subnode.
77
78		    Valid pins are:
79		      gpio0-gpio149
80		        Supports mux, bias and drive-strength
81
82		      sdc2_clk, sdc2_cmd, sdc2_data
83		        Supports bias and drive-strength
84
85		      ufs_reset
86		        Supports bias and drive-strength
87
88- function:
89	Usage: required
90	Value type: <string>
91	Definition: Specify the alternative function to be configured for the
92		    specified pins. Functions are only valid for gpio pins.
93		    Valid values are:
94
95		    gpio, adsp_ext, agera_pll, atest_char, atest_gpsadc0,
96		    atest_gpsadc1, atest_tsens, atest_tsens2, atest_usb1,
97		    atest_usb10, atest_usb11, atest_usb12, atest_usb13,
98		    audio_ref, bimc_dte0, bimc_dte1, blsp10_spi, blsp10_spi_a,
99		    blsp10_spi_b, blsp11_i2c, blsp1_spi, blsp1_spi_a,
100		    blsp1_spi_b, blsp2_spi, blsp9_spi, blsp_i2c1, blsp_i2c2,
101		    blsp_i2c3, blsp_i2c4, blsp_i2c5, blsp_i2c6, blsp_i2c7,
102		    blsp_i2c8, blsp_i2c9, blsp_i2c10, blsp_i2c11, blsp_i2c12,
103		    blsp_spi1, blsp_spi2, blsp_spi3, blsp_spi4, blsp_spi5,
104		    blsp_spi6, blsp_spi7, blsp_spi8, blsp_spi9, blsp_spi10,
105		    blsp_spi11, blsp_spi12, blsp_uart1_a, blsp_uart1_b,
106		    blsp_uart2_a, blsp_uart2_b, blsp_uart3_a, blsp_uart3_b,
107		    blsp_uart7_a, blsp_uart7_b, blsp_uart8, blsp_uart8_a,
108		    blsp_uart8_b, blsp_uart9_a, blsp_uart9_b, blsp_uim1_a,
109		    blsp_uim1_b, blsp_uim2_a, blsp_uim2_b, blsp_uim3_a,
110		    blsp_uim3_b, blsp_uim7_a, blsp_uim7_b, blsp_uim8_a,
111		    blsp_uim8_b, blsp_uim9_a, blsp_uim9_b, bt_reset,
112		    btfm_slimbus, cam_mclk, cci_async, cci_i2c, cci_timer0,
113		    cci_timer1, cci_timer2, cci_timer3, cci_timer4, cri_trng,
114		    cri_trng0, cri_trng1, dbg_out, ddr_bist, edp_hot, edp_lcd,
115		    gcc_gp1_a, gcc_gp1_b, gcc_gp2_a, gcc_gp2_b, gcc_gp3_a,
116		    gcc_gp3_b, hdmi_cec, hdmi_ddc, hdmi_hot, hdmi_rcv,
117		    isense_dbg, jitter_bist, ldo_en, ldo_update, lpass_slimbus,
118		    m_voc, mdp_vsync, mdp_vsync0, mdp_vsync1, mdp_vsync2,
119		    mdp_vsync3, mdp_vsync_a, mdp_vsync_b, modem_tsync, mss_lte,
120		    nav_dr, nav_pps, pa_indicator, pci_e0, phase_flag,
121		    pll_bypassnl, pll_reset, pri_mi2s, pri_mi2s_ws, prng_rosc,
122		    pwr_crypto, pwr_modem, pwr_nav, qdss_cti0_a, qdss_cti0_b,
123		    qdss_cti1_a, qdss_cti1_b, qdss, qlink_enable,
124		    qlink_request, qua_mi2s, sd_card, sd_write, sdc40, sdc41,
125		    sdc42, sdc43, sdc4_clk, sdc4_cmd, sec_mi2s, sp_cmu,
126		    spkr_i2s, ssbi1, ssc_irq, ter_mi2s, tgu_ch0, tgu_ch1,
127		    tsense_pwm1, tsense_pwm2, tsif1_clk, tsif1_data, tsif1_en,
128		    tsif1_error, tsif1_sync, tsif2_clk, tsif2_data, tsif2_en,
129		    tsif2_error, tsif2_sync, uim1_clk, uim1_data, uim1_present,
130		    uim1_reset, uim2_clk, uim2_data, uim2_present, uim2_reset,
131		    uim_batt, usb_phy, vfr_1, vsense_clkout, vsense_data0,
132		    vsense_data1, vsense_mode, wlan1_adc0, wlan1_adc1,
133		    wlan2_adc0, wlan2_adc1,
134
135- bias-disable:
136	Usage: optional
137	Value type: <none>
138	Definition: The specified pins should be configued as no pull.
139
140- bias-pull-down:
141	Usage: optional
142	Value type: <none>
143	Definition: The specified pins should be configued as pull down.
144
145- bias-pull-up:
146	Usage: optional
147	Value type: <none>
148	Definition: The specified pins should be configued as pull up.
149
150- output-high:
151	Usage: optional
152	Value type: <none>
153	Definition: The specified pins are configured in output mode, driven
154		    high.
155		    Not valid for sdc pins.
156
157- output-low:
158	Usage: optional
159	Value type: <none>
160	Definition: The specified pins are configured in output mode, driven
161		    low.
162		    Not valid for sdc pins.
163
164- drive-strength:
165	Usage: optional
166	Value type: <u32>
167	Definition: Selects the drive strength for the specified pins, in mA.
168		    Valid values are: 2, 4, 6, 8, 10, 12, 14 and 16
169
170Example:
171
172	tlmm: pinctrl@03400000 {
173		compatible = "qcom,msm8998-pinctrl";
174		reg = <0x03400000 0xc00000>;
175		interrupts = <0 208 0>;
176		gpio-controller;
177		#gpio-cells = <2>;
178		interrupt-controller;
179		#interrupt-cells = <2>;
180
181		uart_console_active: uart_console_active {
182			mux {
183				pins = "gpio4", "gpio5";
184				function = "blsp_uart8_a";
185			};
186
187			config {
188				pins = "gpio4", "gpio5";
189				drive-strength = <2>;
190				bias-disable;
191			};
192		};
193	};
194