1* Freescale i.MX6 PCIe interface
2
3This PCIe host controller is based on the Synopsys DesignWare PCIe IP
4and thus inherits all the common properties defined in designware-pcie.txt.
5
6Required properties:
7- compatible:
8	- "fsl,imx6q-pcie"
9	- "fsl,imx6sx-pcie",
10	- "fsl,imx6qp-pcie"
11	- "fsl,imx7d-pcie"
12- reg: base address and length of the PCIe controller
13- interrupts: A list of interrupt outputs of the controller. Must contain an
14  entry for each entry in the interrupt-names property.
15- interrupt-names: Must include the following entries:
16	- "msi": The interrupt that is asserted when an MSI is received
17- clock-names: Must include the following additional entries:
18	- "pcie_phy"
19
20Optional properties:
21- fsl,tx-deemph-gen1: Gen1 De-emphasis value. Default: 0
22- fsl,tx-deemph-gen2-3p5db: Gen2 (3.5db) De-emphasis value. Default: 0
23- fsl,tx-deemph-gen2-6db: Gen2 (6db) De-emphasis value. Default: 20
24- fsl,tx-swing-full: Gen2 TX SWING FULL value. Default: 127
25- fsl,tx-swing-low: TX launch amplitude swing_low value. Default: 127
26- fsl,max-link-speed: Specify PCI gen for link capability. Must be '2' for
27  gen2, otherwise will default to gen1. Note that the IMX6 LVDS clock outputs
28  do not meet gen2 jitter requirements and thus for gen2 capability a gen2
29  compliant clock generator should be used and configured.
30- reset-gpio: Should specify the GPIO for controlling the PCI bus device reset
31  signal. It's not polarity aware and defaults to active-low reset sequence
32  (L=reset state, H=operation state).
33- reset-gpio-active-high: If present then the reset sequence using the GPIO
34  specified in the "reset-gpio" property is reversed (H=reset state,
35  L=operation state).
36- vpcie-supply: Should specify the regulator in charge of PCIe port power.
37  The regulator will be enabled when initializing the PCIe host and
38  disabled either as part of the init process or when shutting down the
39  host.
40
41Additional required properties for imx6sx-pcie:
42- clock names: Must include the following additional entries:
43	- "pcie_inbound_axi"
44- power-domains: Must be set to a phandle pointing to the PCIE_PHY power domain
45
46Additional required properties for imx7d-pcie:
47- power-domains: Must be set to a phandle pointing to PCIE_PHY power domain
48- resets: Must contain phandles to PCIe-related reset lines exposed by SRC
49  IP block
50- reset-names: Must contain the following entires:
51	       - "pciephy"
52	       - "apps"
53
54Example:
55
56	pcie@01000000 {
57		compatible = "fsl,imx6q-pcie", "snps,dw-pcie";
58		reg = <0x01ffc000 0x04000>,
59		      <0x01f00000 0x80000>;
60		reg-names = "dbi", "config";
61		#address-cells = <3>;
62		#size-cells = <2>;
63		device_type = "pci";
64		ranges = <0x00000800 0 0x01f00000 0x01f00000 0 0x00080000
65			  0x81000000 0 0          0x01f80000 0 0x00010000
66			  0x82000000 0 0x01000000 0x01000000 0 0x00f00000>;
67		num-lanes = <1>;
68		interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
69		interrupt-names = "msi";
70		#interrupt-cells = <1>;
71		interrupt-map-mask = <0 0 0 0x7>;
72		interrupt-map = <0 0 0 1 &intc GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
73		                <0 0 0 2 &intc GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>,
74		                <0 0 0 3 &intc GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
75		                <0 0 0 4 &intc GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
76		clocks = <&clks 144>, <&clks 206>, <&clks 189>;
77		clock-names = "pcie", "pcie_bus", "pcie_phy";
78	};
79