1Freescale i.MX6 On-Chip OTP Controller (OCOTP) device tree bindings
2
3This binding represents the on-chip eFuse OTP controller found on
4i.MX6Q/D, i.MX6DL/S, i.MX6SL, i.MX6SX, i.MX6UL and i.MX6SLL SoCs.
5
6Required properties:
7- compatible: should be one of
8	"fsl,imx6q-ocotp" (i.MX6Q/D/DL/S),
9	"fsl,imx6sl-ocotp" (i.MX6SL), or
10	"fsl,imx6sx-ocotp" (i.MX6SX),
11	"fsl,imx6ul-ocotp" (i.MX6UL),
12	"fsl,imx7d-ocotp" (i.MX7D/S),
13	"fsl,imx6sll-ocotp" (i.MX6SLL),
14	followed by "syscon".
15- #address-cells : Should be 1
16- #size-cells : Should be 1
17- reg: Should contain the register base and length.
18- clocks: Should contain a phandle pointing to the gated peripheral clock.
19
20Optional properties:
21- read-only: disable write access
22
23Optional Child nodes:
24
25- Data cells of ocotp:
26  Detailed bindings are described in bindings/nvmem/nvmem.txt
27
28Example:
29	ocotp: ocotp@21bc000 {
30		#address-cells = <1>;
31		#size-cells = <1>;
32		compatible = "fsl,imx6sx-ocotp", "syscon";
33		reg = <0x021bc000 0x4000>;
34		clocks = <&clks IMX6SX_CLK_OCOTP>;
35
36		tempmon_calib: calib@38 {
37			reg = <0x38 4>;
38		};
39
40		tempmon_temp_grade: temp-grade@20 {
41			reg = <0x20 4>;
42		};
43	};
44