1* Marvell Armada 375 Ethernet Controller (PPv2.1) 2 Marvell Armada 7K/8K Ethernet Controller (PPv2.2) 3 4Required properties: 5 6- compatible: should be one of: 7 "marvell,armada-375-pp2" 8 "marvell,armada-7k-pp2" 9- reg: addresses and length of the register sets for the device. 10 For "marvell,armada-375-pp2", must contain the following register 11 sets: 12 - common controller registers 13 - LMS registers 14 - one register area per Ethernet port 15 For "marvell,armada-7k-pp2", must contain the following register 16 sets: 17 - packet processor registers 18 - networking interfaces registers 19 20- clocks: pointers to the reference clocks for this device, consequently: 21 - main controller clock (for both armada-375-pp2 and armada-7k-pp2) 22 - GOP clock (for both armada-375-pp2 and armada-7k-pp2) 23 - MG clock (only for armada-7k-pp2) 24 - MG Core clock (only for armada-7k-pp2) 25 - AXI clock (only for armada-7k-pp2) 26- clock-names: names of used clocks, must be "pp_clk", "gop_clk", "mg_clk", 27 "mg_core_clk" and "axi_clk" (the 3 latter only for armada-7k-pp2). 28 29The ethernet ports are represented by subnodes. At least one port is 30required. 31 32Required properties (port): 33 34- interrupts: interrupt for the port 35- port-id: ID of the port from the MAC point of view 36- gop-port-id: only for marvell,armada-7k-pp2, ID of the port from the 37 GOP (Group Of Ports) point of view. This ID is used to index the 38 per-port registers in the second register area. 39- phy-mode: See ethernet.txt file in the same directory 40 41Optional properties (port): 42 43- marvell,loopback: port is loopback mode 44- phy: a phandle to a phy node defining the PHY address (as the reg 45 property, a single integer). 46- interrupt-names: if more than a single interrupt for rx is given, must 47 be the name associated to the interrupts listed. Valid 48 names are: "tx-cpu0", "tx-cpu1", "tx-cpu2", "tx-cpu3", 49 "rx-shared", "link". 50- marvell,system-controller: a phandle to the system controller. 51 52Example for marvell,armada-375-pp2: 53 54ethernet@f0000 { 55 compatible = "marvell,armada-375-pp2"; 56 reg = <0xf0000 0xa000>, 57 <0xc0000 0x3060>, 58 <0xc4000 0x100>, 59 <0xc5000 0x100>; 60 clocks = <&gateclk 3>, <&gateclk 19>; 61 clock-names = "pp_clk", "gop_clk"; 62 63 eth0: eth0@c4000 { 64 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; 65 port-id = <0>; 66 phy = <&phy0>; 67 phy-mode = "gmii"; 68 }; 69 70 eth1: eth1@c5000 { 71 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>; 72 port-id = <1>; 73 phy = <&phy3>; 74 phy-mode = "gmii"; 75 }; 76}; 77 78Example for marvell,armada-7k-pp2: 79 80cpm_ethernet: ethernet@0 { 81 compatible = "marvell,armada-7k-pp22"; 82 reg = <0x0 0x100000>, <0x129000 0xb000>; 83 clocks = <&cpm_syscon0 1 3>, <&cpm_syscon0 1 9>, 84 <&cpm_syscon0 1 5>, <&cpm_syscon0 1 6>, <&cpm_syscon0 1 18>; 85 clock-names = "pp_clk", "gop_clk", "mg_clk", "mg_core_clk", "axi_clk"; 86 87 eth0: eth0 { 88 interrupts = <ICU_GRP_NSR 39 IRQ_TYPE_LEVEL_HIGH>, 89 <ICU_GRP_NSR 43 IRQ_TYPE_LEVEL_HIGH>, 90 <ICU_GRP_NSR 47 IRQ_TYPE_LEVEL_HIGH>, 91 <ICU_GRP_NSR 51 IRQ_TYPE_LEVEL_HIGH>, 92 <ICU_GRP_NSR 55 IRQ_TYPE_LEVEL_HIGH>; 93 interrupt-names = "tx-cpu0", "tx-cpu1", "tx-cpu2", 94 "tx-cpu3", "rx-shared"; 95 port-id = <0>; 96 gop-port-id = <0>; 97 }; 98 99 eth1: eth1 { 100 interrupts = <ICU_GRP_NSR 40 IRQ_TYPE_LEVEL_HIGH>, 101 <ICU_GRP_NSR 44 IRQ_TYPE_LEVEL_HIGH>, 102 <ICU_GRP_NSR 48 IRQ_TYPE_LEVEL_HIGH>, 103 <ICU_GRP_NSR 52 IRQ_TYPE_LEVEL_HIGH>, 104 <ICU_GRP_NSR 56 IRQ_TYPE_LEVEL_HIGH>; 105 interrupt-names = "tx-cpu0", "tx-cpu1", "tx-cpu2", 106 "tx-cpu3", "rx-shared"; 107 port-id = <1>; 108 gop-port-id = <2>; 109 }; 110 111 eth2: eth2 { 112 interrupts = <ICU_GRP_NSR 41 IRQ_TYPE_LEVEL_HIGH>, 113 <ICU_GRP_NSR 45 IRQ_TYPE_LEVEL_HIGH>, 114 <ICU_GRP_NSR 49 IRQ_TYPE_LEVEL_HIGH>, 115 <ICU_GRP_NSR 53 IRQ_TYPE_LEVEL_HIGH>, 116 <ICU_GRP_NSR 57 IRQ_TYPE_LEVEL_HIGH>; 117 interrupt-names = "tx-cpu0", "tx-cpu1", "tx-cpu2", 118 "tx-cpu3", "rx-shared"; 119 port-id = <2>; 120 gop-port-id = <3>; 121 }; 122}; 123