1* Cadence SD/SDIO/eMMC Host Controller
2
3Required properties:
4- compatible: should be one of the following:
5    "cdns,sd4hc"               - default of the IP
6    "socionext,uniphier-sd4hc" - for Socionext UniPhier SoCs
7- reg: offset and length of the register set for the device.
8- interrupts: a single interrupt specifier.
9- clocks: phandle to the input clock.
10
11Optional properties:
12For eMMC configuration, supported speed modes are not indicated by the SDHCI
13Capabilities Register.  Instead, the following properties should be specified
14if supported.  See mmc.txt for details.
15- mmc-ddr-1_8v
16- mmc-ddr-1_2v
17- mmc-hs200-1_8v
18- mmc-hs200-1_2v
19- mmc-hs400-1_8v
20- mmc-hs400-1_2v
21
22Some PHY delays can be configured by following properties.
23PHY DLL input delays:
24They are used to delay the data valid window, and align the window
25to sampling clock. The delay starts from 5ns (for delay parameter equal to 0)
26and it is increased by 2.5ns in each step.
27- cdns,phy-input-delay-sd-highspeed:
28  Value of the delay in the input path for SD high-speed timing
29  Valid range = [0:0x1F].
30- cdns,phy-input-delay-legacy:
31  Value of the delay in the input path for legacy timing
32  Valid range = [0:0x1F].
33- cdns,phy-input-delay-sd-uhs-sdr12:
34  Value of the delay in the input path for SD UHS SDR12 timing
35  Valid range = [0:0x1F].
36- cdns,phy-input-delay-sd-uhs-sdr25:
37  Value of the delay in the input path for SD UHS SDR25 timing
38  Valid range = [0:0x1F].
39- cdns,phy-input-delay-sd-uhs-sdr50:
40  Value of the delay in the input path for SD UHS SDR50 timing
41  Valid range = [0:0x1F].
42- cdns,phy-input-delay-sd-uhs-ddr50:
43  Value of the delay in the input path for SD UHS DDR50 timing
44  Valid range = [0:0x1F].
45- cdns,phy-input-delay-mmc-highspeed:
46  Value of the delay in the input path for MMC high-speed timing
47  Valid range = [0:0x1F].
48- cdns,phy-input-delay-mmc-ddr:
49  Value of the delay in the input path for eMMC high-speed DDR timing
50  Valid range = [0:0x1F].
51
52PHY DLL clock delays:
53Each delay property represents the fraction of the clock period.
54The approximate delay value will be
55(<delay property value>/128)*sdmclk_clock_period.
56- cdns,phy-dll-delay-sdclk:
57  Value of the delay introduced on the sdclk output
58  for all modes except HS200, HS400 and HS400_ES.
59  Valid range = [0:0x7F].
60- cdns,phy-dll-delay-sdclk-hsmmc:
61  Value of the delay introduced on the sdclk output
62  for HS200, HS400 and HS400_ES speed modes.
63  Valid range = [0:0x7F].
64- cdns,phy-dll-delay-strobe:
65  Value of the delay introduced on the dat_strobe input
66  used in HS400 / HS400_ES speed modes.
67  Valid range = [0:0x7F].
68
69Example:
70	emmc: sdhci@5a000000 {
71		compatible = "socionext,uniphier-sd4hc", "cdns,sd4hc";
72		reg = <0x5a000000 0x400>;
73		interrupts = <0 78 4>;
74		clocks = <&clk 4>;
75		bus-width = <8>;
76		mmc-ddr-1_8v;
77		mmc-hs200-1_8v;
78		mmc-hs400-1_8v;
79		cdns,phy-dll-delay-sdclk = <0>;
80	};
81