1Common bindings for video receiver and transmitter interfaces 2 3General concept 4--------------- 5 6Video data pipelines usually consist of external devices, e.g. camera sensors, 7controlled over an I2C, SPI or UART bus, and SoC internal IP blocks, including 8video DMA engines and video data processors. 9 10SoC internal blocks are described by DT nodes, placed similarly to other SoC 11blocks. External devices are represented as child nodes of their respective 12bus controller nodes, e.g. I2C. 13 14Data interfaces on all video devices are described by their child 'port' nodes. 15Configuration of a port depends on other devices participating in the data 16transfer and is described by 'endpoint' subnodes. 17 18device { 19 ... 20 ports { 21 #address-cells = <1>; 22 #size-cells = <0>; 23 24 port@0 { 25 ... 26 endpoint@0 { ... }; 27 endpoint@1 { ... }; 28 }; 29 port@1 { ... }; 30 }; 31}; 32 33If a port can be configured to work with more than one remote device on the same 34bus, an 'endpoint' child node must be provided for each of them. If more than 35one port is present in a device node or there is more than one endpoint at a 36port, or port node needs to be associated with a selected hardware interface, 37a common scheme using '#address-cells', '#size-cells' and 'reg' properties is 38used. 39 40All 'port' nodes can be grouped under optional 'ports' node, which allows to 41specify #address-cells, #size-cells properties independently for the 'port' 42and 'endpoint' nodes and any child device nodes a device might have. 43 44Two 'endpoint' nodes are linked with each other through their 'remote-endpoint' 45phandles. An endpoint subnode of a device contains all properties needed for 46configuration of this device for data exchange with other device. In most 47cases properties at the peer 'endpoint' nodes will be identical, however they 48might need to be different when there is any signal modifications on the bus 49between two devices, e.g. there are logic signal inverters on the lines. 50 51It is allowed for multiple endpoints at a port to be active simultaneously, 52where supported by a device. For example, in case where a data interface of 53a device is partitioned into multiple data busses, e.g. 16-bit input port 54divided into two separate ITU-R BT.656 8-bit busses. In such case bus-width 55and data-shift properties can be used to assign physical data lines to each 56endpoint node (logical bus). 57 58Documenting bindings for devices 59-------------------------------- 60 61All required and optional bindings the device supports shall be explicitly 62documented in device DT binding documentation. This also includes port and 63endpoint nodes for the device, including unit-addresses and reg properties where 64relevant. 65 66Please also see Documentation/devicetree/bindings/graph.txt . 67 68Required properties 69------------------- 70 71If there is more than one 'port' or more than one 'endpoint' node or 'reg' 72property is present in port and/or endpoint nodes the following properties 73are required in a relevant parent node: 74 75 - #address-cells : number of cells required to define port/endpoint 76 identifier, should be 1. 77 - #size-cells : should be zero. 78 79 80Optional properties 81------------------- 82 83- flash-leds: An array of phandles, each referring to a flash LED, a sub-node 84 of the LED driver device node. 85 86- lens-focus: A phandle to the node of the focus lens controller. 87 88- rotation: The device, typically an image sensor, is not mounted upright, 89 but a number of degrees counter clockwise. Typical values are 0 and 180 90 (upside down). 91 92 93Optional endpoint properties 94---------------------------- 95 96- remote-endpoint: phandle to an 'endpoint' subnode of a remote device node. 97- slave-mode: a boolean property indicating that the link is run in slave mode. 98 The default when this property is not specified is master mode. In the slave 99 mode horizontal and vertical synchronization signals are provided to the 100 slave device (data source) by the master device (data sink). In the master 101 mode the data source device is also the source of the synchronization signals. 102- bus-type: data bus type. Possible values are: 103 0 - autodetect based on other properties (MIPI CSI-2 D-PHY, parallel or Bt656) 104 1 - MIPI CSI-2 C-PHY 105 2 - MIPI CSI1 106 3 - CCP2 107- bus-width: number of data lines actively used, valid for the parallel busses. 108- data-shift: on the parallel data busses, if bus-width is used to specify the 109 number of data lines, data-shift can be used to specify which data lines are 110 used, e.g. "bus-width=<8>; data-shift=<2>;" means, that lines 9:2 are used. 111- hsync-active: active state of the HSYNC signal, 0/1 for LOW/HIGH respectively. 112- vsync-active: active state of the VSYNC signal, 0/1 for LOW/HIGH respectively. 113 Note, that if HSYNC and VSYNC polarities are not specified, embedded 114 synchronization may be required, where supported. 115- data-active: similar to HSYNC and VSYNC, specifies data line polarity. 116- data-enable-active: similar to HSYNC and VSYNC, specifies the data enable 117 signal polarity. 118- field-even-active: field signal level during the even field data transmission. 119- pclk-sample: sample data on rising (1) or falling (0) edge of the pixel clock 120 signal. 121- sync-on-green-active: active state of Sync-on-green (SoG) signal, 0/1 for 122 LOW/HIGH respectively. 123- data-lanes: an array of physical data lane indexes. Position of an entry 124 determines the logical lane number, while the value of an entry indicates 125 physical lane, e.g. for 2-lane MIPI CSI-2 bus we could have 126 "data-lanes = <1 2>;", assuming the clock lane is on hardware lane 0. 127 If the hardware does not support lane reordering, monotonically 128 incremented values shall be used from 0 or 1 onwards, depending on 129 whether or not there is also a clock lane. This property is valid for 130 serial busses only (e.g. MIPI CSI-2). 131- clock-lanes: an array of physical clock lane indexes. Position of an entry 132 determines the logical lane number, while the value of an entry indicates 133 physical lane, e.g. for a MIPI CSI-2 bus we could have "clock-lanes = <0>;", 134 which places the clock lane on hardware lane 0. This property is valid for 135 serial busses only (e.g. MIPI CSI-2). Note that for the MIPI CSI-2 bus this 136 array contains only one entry. 137- clock-noncontinuous: a boolean property to allow MIPI CSI-2 non-continuous 138 clock mode. 139- link-frequencies: Allowed data bus frequencies. For MIPI CSI-2, for 140 instance, this is the actual frequency of the bus, not bits per clock per 141 lane value. An array of 64-bit unsigned integers. 142- lane-polarities: an array of polarities of the lanes starting from the clock 143 lane and followed by the data lanes in the same order as in data-lanes. 144 Valid values are 0 (normal) and 1 (inverted). The length of the array 145 should be the combined length of data-lanes and clock-lanes properties. 146 If the lane-polarities property is omitted, the value must be interpreted 147 as 0 (normal). This property is valid for serial busses only. 148- strobe: Whether the clock signal is used as clock (0) or strobe (1). Used 149 with CCP2, for instance. 150 151Example 152------- 153 154The example snippet below describes two data pipelines. ov772x and imx074 are 155camera sensors with a parallel and serial (MIPI CSI-2) video bus respectively. 156Both sensors are on the I2C control bus corresponding to the i2c0 controller 157node. ov772x sensor is linked directly to the ceu0 video host interface. 158imx074 is linked to ceu0 through the MIPI CSI-2 receiver (csi2). ceu0 has a 159(single) DMA engine writing captured data to memory. ceu0 node has a single 160'port' node which may indicate that at any time only one of the following data 161pipelines can be active: ov772x -> ceu0 or imx074 -> csi2 -> ceu0. 162 163 ceu0: ceu@fe910000 { 164 compatible = "renesas,sh-mobile-ceu"; 165 reg = <0xfe910000 0xa0>; 166 interrupts = <0x880>; 167 168 mclk: master_clock { 169 compatible = "renesas,ceu-clock"; 170 #clock-cells = <1>; 171 clock-frequency = <50000000>; /* Max clock frequency */ 172 clock-output-names = "mclk"; 173 }; 174 175 port { 176 #address-cells = <1>; 177 #size-cells = <0>; 178 179 /* Parallel bus endpoint */ 180 ceu0_1: endpoint@1 { 181 reg = <1>; /* Local endpoint # */ 182 remote = <&ov772x_1_1>; /* Remote phandle */ 183 bus-width = <8>; /* Used data lines */ 184 data-shift = <2>; /* Lines 9:2 are used */ 185 186 /* If hsync-active/vsync-active are missing, 187 embedded BT.656 sync is used */ 188 hsync-active = <0>; /* Active low */ 189 vsync-active = <0>; /* Active low */ 190 data-active = <1>; /* Active high */ 191 pclk-sample = <1>; /* Rising */ 192 }; 193 194 /* MIPI CSI-2 bus endpoint */ 195 ceu0_0: endpoint@0 { 196 reg = <0>; 197 remote = <&csi2_2>; 198 }; 199 }; 200 }; 201 202 i2c0: i2c@fff20000 { 203 ... 204 ov772x_1: camera@21 { 205 compatible = "ovti,ov772x"; 206 reg = <0x21>; 207 vddio-supply = <®ulator1>; 208 vddcore-supply = <®ulator2>; 209 210 clock-frequency = <20000000>; 211 clocks = <&mclk 0>; 212 clock-names = "xclk"; 213 214 port { 215 /* With 1 endpoint per port no need for addresses. */ 216 ov772x_1_1: endpoint { 217 bus-width = <8>; 218 remote-endpoint = <&ceu0_1>; 219 hsync-active = <1>; 220 vsync-active = <0>; /* Who came up with an 221 inverter here ?... */ 222 data-active = <1>; 223 pclk-sample = <1>; 224 }; 225 }; 226 }; 227 228 imx074: camera@1a { 229 compatible = "sony,imx074"; 230 reg = <0x1a>; 231 vddio-supply = <®ulator1>; 232 vddcore-supply = <®ulator2>; 233 234 clock-frequency = <30000000>; /* Shared clock with ov772x_1 */ 235 clocks = <&mclk 0>; 236 clock-names = "sysclk"; /* Assuming this is the 237 name in the datasheet */ 238 port { 239 imx074_1: endpoint { 240 clock-lanes = <0>; 241 data-lanes = <1 2>; 242 remote-endpoint = <&csi2_1>; 243 }; 244 }; 245 }; 246 }; 247 248 csi2: csi2@ffc90000 { 249 compatible = "renesas,sh-mobile-csi2"; 250 reg = <0xffc90000 0x1000>; 251 interrupts = <0x17a0>; 252 #address-cells = <1>; 253 #size-cells = <0>; 254 255 port@1 { 256 compatible = "renesas,csi2c"; /* One of CSI2I and CSI2C. */ 257 reg = <1>; /* CSI-2 PHY #1 of 2: PHY_S, 258 PHY_M has port address 0, 259 is unused. */ 260 csi2_1: endpoint { 261 clock-lanes = <0>; 262 data-lanes = <2 1>; 263 remote-endpoint = <&imx074_1>; 264 }; 265 }; 266 port@2 { 267 reg = <2>; /* port 2: link to the CEU */ 268 269 csi2_2: endpoint { 270 remote-endpoint = <&ceu0_0>; 271 }; 272 }; 273 }; 274