1Samsung Exynos IOMMU H/W, System MMU (System Memory Management Unit)
2
3Samsung's Exynos architecture contains System MMUs that enables scattered
4physical memory chunks visible as a contiguous region to DMA-capable peripheral
5devices like MFC, FIMC, FIMD, GScaler, FIMC-IS and so forth.
6
7System MMU is an IOMMU and supports identical translation table format to
8ARMv7 translation tables with minimum set of page properties including access
9permissions, shareability and security protection. In addition, System MMU has
10another capabilities like L2 TLB or block-fetch buffers to minimize translation
11latency.
12
13System MMUs are in many to one relation with peripheral devices, i.e. single
14peripheral device might have multiple System MMUs (usually one for each bus
15master), but one System MMU can handle transactions from only one peripheral
16device. The relation between a System MMU and the peripheral device needs to be
17defined in device node of the peripheral device.
18
19MFC in all Exynos SoCs and FIMD, M2M Scalers and G2D in Exynos5420 has 2 System
20MMUs.
21* MFC has one System MMU on its left and right bus.
22* FIMD in Exynos5420 has one System MMU for window 0 and 4, the other system MMU
23  for window 1, 2 and 3.
24* M2M Scalers and G2D in Exynos5420 has one System MMU on the read channel and
25  the other System MMU on the write channel.
26
27For information on assigning System MMU controller to its peripheral devices,
28see generic IOMMU bindings.
29
30Required properties:
31- compatible: Should be "samsung,exynos-sysmmu"
32- reg: A tuple of base address and size of System MMU registers.
33- #iommu-cells: Should be <0>.
34- interrupts: An interrupt specifier for interrupt signal of System MMU,
35	      according to the format defined by a particular interrupt
36	      controller.
37- clock-names: Should be "sysmmu" or a pair of "aclk" and "pclk" to gate
38	       SYSMMU core clocks.
39	       Optional "master" if the clock to the System MMU is gated by
40	       another gate clock other core  (usually main gate clock
41	       of peripheral device this SYSMMU belongs to).
42- clocks: Phandles for respective clocks described by clock-names.
43- power-domains: Required if the System MMU is needed to gate its power.
44	  Please refer to the following document:
45	  Documentation/devicetree/bindings/power/pd-samsung.txt
46
47Examples:
48	gsc_0: gsc@13e00000 {
49		compatible = "samsung,exynos5-gsc";
50		reg = <0x13e00000 0x1000>;
51		interrupts = <0 85 0>;
52		power-domains = <&pd_gsc>;
53		clocks = <&clock CLK_GSCL0>;
54		clock-names = "gscl";
55		iommus = <&sysmmu_gsc0>;
56	};
57
58	sysmmu_gsc0: sysmmu@13e80000 {
59		compatible = "samsung,exynos-sysmmu";
60		reg = <0x13E80000 0x1000>;
61		interrupt-parent = <&combiner>;
62		interrupts = <2 0>;
63		clock-names = "sysmmu", "master";
64		clocks = <&clock CLK_SMMU_GSCL0>, <&clock CLK_GSCL0>;
65		power-domains = <&pd_gsc>;
66		#iommu-cells = <0>;
67	};
68