1* Mediatek IOMMU Architecture Implementation
2
3  Some Mediatek SOCs contain a Multimedia Memory Management Unit (M4U), and
4this M4U have two generations of HW architecture. Generation one uses flat
5pagetable, and only supports 4K size page mapping. Generation two uses the
6ARM Short-Descriptor translation table format for address translation.
7
8  About the M4U Hardware Block Diagram, please check below:
9
10              EMI (External Memory Interface)
11               |
12              m4u (Multimedia Memory Management Unit)
13               |
14           SMI Common(Smart Multimedia Interface Common)
15               |
16       +----------------+-------
17       |                |
18       |                |
19   SMI larb0        SMI larb1   ... SoCs have several SMI local arbiter(larb).
20   (display)         (vdec)
21       |                |
22       |                |
23 +-----+-----+     +----+----+
24 |     |     |     |    |    |
25 |     |     |...  |    |    |  ... There are different ports in each larb.
26 |     |     |     |    |    |
27OVL0 RDMA0 WDMA0  MC   PP   VLD
28
29  As above, The Multimedia HW will go through SMI and M4U while it
30access EMI. SMI is a bridge between m4u and the Multimedia HW. It contain
31smi local arbiter and smi common. It will control whether the Multimedia
32HW should go though the m4u for translation or bypass it and talk
33directly with EMI. And also SMI help control the power domain and clocks for
34each local arbiter.
35  Normally we specify a local arbiter(larb) for each multimedia HW
36like display, video decode, and camera. And there are different ports
37in each larb. Take a example, There are many ports like MC, PP, VLD in the
38video decode local arbiter, all these ports are according to the video HW.
39
40Required properties:
41- compatible : must be one of the following string:
42	"mediatek,mt2701-m4u" for mt2701 which uses generation one m4u HW.
43	"mediatek,mt2712-m4u" for mt2712 which uses generation two m4u HW.
44	"mediatek,mt8173-m4u" for mt8173 which uses generation two m4u HW.
45- reg : m4u register base and size.
46- interrupts : the interrupt of m4u.
47- clocks : must contain one entry for each clock-names.
48- clock-names : must be "bclk", It is the block clock of m4u.
49- mediatek,larbs : List of phandle to the local arbiters in the current Socs.
50	Refer to bindings/memory-controllers/mediatek,smi-larb.txt. It must sort
51	according to the local arbiter index, like larb0, larb1, larb2...
52- iommu-cells : must be 1. This is the mtk_m4u_id according to the HW.
53	Specifies the mtk_m4u_id as defined in
54	dt-binding/memory/mt2701-larb-port.h for mt2701,
55	dt-binding/memory/mt2712-larb-port.h for mt2712, and
56	dt-binding/memory/mt8173-larb-port.h for mt8173.
57
58Example:
59	iommu: iommu@10205000 {
60		compatible = "mediatek,mt8173-m4u";
61		reg = <0 0x10205000 0 0x1000>;
62		interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_LOW>;
63		clocks = <&infracfg CLK_INFRA_M4U>;
64		clock-names = "bclk";
65		mediatek,larbs = <&larb0 &larb1 &larb2 &larb3 &larb4 &larb5>;
66		#iommu-cells = <1>;
67	};
68
69Example for a client device:
70	display {
71		compatible = "mediatek,mt8173-disp";
72		iommus = <&iommu M4U_PORT_DISP_OVL0>,
73			 <&iommu M4U_PORT_DISP_RDMA0>;
74		...
75	};
76