1STMicroelectronics STM32 DAC
2
3The STM32 DAC is a 12-bit voltage output digital-to-analog converter. The DAC
4may be configured in 8 or 12-bit mode. It has two output channels, each with
5its own converter.
6It has built-in noise and triangle waveform generator and supports external
7triggers for conversions. The DAC's output buffer allows a high drive output
8current.
9
10Contents of a stm32 dac root node:
11-----------------------------------
12Required properties:
13- compatible: Should be one of:
14  "st,stm32f4-dac-core"
15  "st,stm32h7-dac-core"
16- reg: Offset and length of the device's register set.
17- clocks: Must contain an entry for pclk (which feeds the peripheral bus
18  interface)
19- clock-names: Must be "pclk".
20- vref-supply: Phandle to the vref+ input analog reference supply.
21- #address-cells = <1>;
22- #size-cells = <0>;
23
24Optional properties:
25- resets: Must contain the phandle to the reset controller.
26- A pinctrl state named "default" for each DAC channel may be defined to set
27  DAC_OUTx pin in mode of operation for analog output on external pin.
28
29Contents of a stm32 dac child node:
30-----------------------------------
31DAC core node should contain at least one subnode, representing a
32DAC instance/channel available on the machine.
33
34Required properties:
35- compatible: Must be "st,stm32-dac".
36- reg: Must be either 1 or 2, to define (single) channel in use
37- #io-channel-cells = <1>: See the IIO bindings section "IIO consumers" in
38  Documentation/devicetree/bindings/iio/iio-bindings.txt
39
40Example:
41	dac: dac@40007400 {
42		compatible = "st,stm32h7-dac-core";
43		reg = <0x40007400 0x400>;
44		clocks = <&clk>;
45		clock-names = "pclk";
46		vref-supply = <&reg_vref>;
47		pinctrl-names = "default";
48		pinctrl-0 = <&dac_out1 &dac_out2>;
49		#address-cells = <1>;
50		#size-cells = <0>;
51
52		dac1: dac@1 {
53			compatible = "st,stm32-dac";
54			#io-channels-cells = <1>;
55			reg = <1>;
56		};
57
58		dac2: dac@2 {
59			compatible = "st,stm32-dac";
60			#io-channels-cells = <1>;
61			reg = <2>;
62		};
63	};
64