1STMicroelectronics STM32 ADC device driver
2
3STM32 ADC is a successive approximation analog-to-digital converter.
4It has several multiplexed input channels. Conversions can be performed
5in single, continuous, scan or discontinuous mode. Result of the ADC is
6stored in a left-aligned or right-aligned 32-bit data register.
7Conversions can be launched in software or using hardware triggers.
8
9The analog watchdog feature allows the application to detect if the input
10voltage goes beyond the user-defined, higher or lower thresholds.
11
12Each STM32 ADC block can have up to 3 ADC instances.
13
14Each instance supports two contexts to manage conversions, each one has its
15own configurable sequence and trigger:
16- regular conversion can be done in sequence, running in background
17- injected conversions have higher priority, and so have the ability to
18  interrupt regular conversion sequence (either triggered in SW or HW).
19  Regular sequence is resumed, in case it has been interrupted.
20
21Contents of a stm32 adc root node:
22-----------------------------------
23Required properties:
24- compatible: Should be one of:
25  "st,stm32f4-adc-core"
26  "st,stm32h7-adc-core"
27  "st,stm32mp1-adc-core"
28- reg: Offset and length of the ADC block register set.
29- interrupts: One or more interrupts for ADC block. Some parts like stm32f4
30  and stm32h7 share a common ADC interrupt line. stm32mp1 has two separate
31  interrupt lines, one for each ADC within ADC block.
32- clocks: Core can use up to two clocks, depending on part used:
33  - "adc" clock: for the analog circuitry, common to all ADCs.
34    It's required on stm32f4.
35    It's optional on stm32h7.
36  - "bus" clock: for registers access, common to all ADCs.
37    It's not present on stm32f4.
38    It's required on stm32h7.
39- clock-names: Must be "adc" and/or "bus" depending on part used.
40- interrupt-controller: Identifies the controller node as interrupt-parent
41- vref-supply: Phandle to the vref input analog reference voltage.
42- #interrupt-cells = <1>;
43- #address-cells = <1>;
44- #size-cells = <0>;
45
46Optional properties:
47- A pinctrl state named "default" for each ADC channel may be defined to set
48  inX ADC pins in mode of operation for analog input on external pin.
49
50Contents of a stm32 adc child node:
51-----------------------------------
52An ADC block node should contain at least one subnode, representing an
53ADC instance available on the machine.
54
55Required properties:
56- compatible: Should be one of:
57  "st,stm32f4-adc"
58  "st,stm32h7-adc"
59  "st,stm32mp1-adc"
60- reg: Offset of ADC instance in ADC block (e.g. may be 0x0, 0x100, 0x200).
61- clocks: Input clock private to this ADC instance. It's required only on
62  stm32f4, that has per instance clock input for registers access.
63- interrupts: IRQ Line for the ADC (e.g. may be 0 for adc@0, 1 for adc@100 or
64  2 for adc@200).
65- st,adc-channels: List of single-ended channels muxed for this ADC.
66  It can have up to 16 channels on stm32f4 or 20 channels on stm32h7, numbered
67  from 0 to 15 or 19 (resp. for in0..in15 or in0..in19).
68- st,adc-diff-channels: List of differential channels muxed for this ADC.
69  Depending on part used, some channels can be configured as differential
70  instead of single-ended (e.g. stm32h7). List here positive and negative
71  inputs pairs as <vinp vinn>, <vinp vinn>,... vinp and vinn are numbered
72  from 0 to 19 on stm32h7)
73  Note: At least one of "st,adc-channels" or "st,adc-diff-channels" is required.
74  Both properties can be used together. Some channels can be used as
75  single-ended and some other ones as differential (mixed). But channels
76  can't be configured both as single-ended and differential (invalid).
77- #io-channel-cells = <1>: See the IIO bindings section "IIO consumers" in
78  Documentation/devicetree/bindings/iio/iio-bindings.txt
79
80Optional properties:
81- dmas: Phandle to dma channel for this ADC instance.
82  See ../../dma/dma.txt for details.
83- dma-names: Must be "rx" when dmas property is being used.
84- assigned-resolution-bits: Resolution (bits) to use for conversions. Must
85  match device available resolutions:
86  * can be 6, 8, 10 or 12 on stm32f4
87  * can be 8, 10, 12, 14 or 16 on stm32h7
88  Default is maximum resolution if unset.
89- st,min-sample-time-nsecs: Minimum sampling time in nanoseconds.
90  Depending on hardware (board) e.g. high/low analog input source impedance,
91  fine tune of ADC sampling time may be recommended.
92  This can be either one value or an array that matches 'st,adc-channels' list,
93  to set sample time resp. for all channels, or independently for each channel.
94
95Example:
96	adc: adc@40012000 {
97		compatible = "st,stm32f4-adc-core";
98		reg = <0x40012000 0x400>;
99		interrupts = <18>;
100		clocks = <&rcc 0 168>;
101		clock-names = "adc";
102		vref-supply = <&reg_vref>;
103		interrupt-controller;
104		pinctrl-names = "default";
105		pinctrl-0 = <&adc3_in8_pin>;
106
107		#interrupt-cells = <1>;
108		#address-cells = <1>;
109		#size-cells = <0>;
110
111		adc@0 {
112			compatible = "st,stm32f4-adc";
113			#io-channel-cells = <1>;
114			reg = <0x0>;
115			clocks = <&rcc 0 168>;
116			interrupt-parent = <&adc>;
117			interrupts = <0>;
118			st,adc-channels = <8>;
119			dmas = <&dma2 0 0 0x400 0x0>;
120			dma-names = "rx";
121			assigned-resolution-bits = <8>;
122		};
123		...
124		other adc child nodes follow...
125	};
126
127Example to setup:
128- channel 1 as single-ended
129- channels 2 & 3 as differential (with resp. 6 & 7 negative inputs)
130
131	adc: adc@40022000 {
132		compatible = "st,stm32h7-adc-core";
133		...
134		adc1: adc@0 {
135			compatible = "st,stm32h7-adc";
136			...
137			st,adc-channels = <1>;
138			st,adc-diff-channels = <2 6>, <3 7>;
139		};
140	};
141