1Xilinx LogiCORE Partial Reconfig Decoupler Softcore
2
3The Xilinx LogiCORE Partial Reconfig Decoupler manages one or more
4decouplers / fpga bridges.
5The controller can decouple/disable the bridges which prevents signal
6changes from passing through the bridge.  The controller can also
7couple / enable the bridges which allows traffic to pass through the
8bridge normally.
9
10The Driver supports only MMIO handling. A PR region can have multiple
11PR Decouplers which can be handled independently or chained via decouple/
12decouple_status signals.
13
14Required properties:
15- compatible		: Should contain "xlnx,pr-decoupler-1.00" followed by
16                          "xlnx,pr-decoupler"
17- regs			: base address and size for decoupler module
18- clocks		: input clock to IP
19- clock-names		: should contain "aclk"
20
21Optional properties:
22- bridge-enable		: 0 if driver should disable bridge at startup
23			  1 if driver should enable bridge at startup
24			  Default is to leave bridge in current state.
25
26See Documentation/devicetree/bindings/fpga/fpga-region.txt for generic bindings.
27
28Example:
29	fpga-bridge@100000450 {
30		compatible = "xlnx,pr-decoupler-1.00",
31			     "xlnx-pr-decoupler";
32		regs = <0x10000045 0x10>;
33		clocks = <&clkc 15>;
34		clock-names = "aclk";
35		bridge-enable = <0>;
36	};
37