1* Synopsys Designware DMA Controller
2
3Required properties:
4- compatible: "snps,dma-spear1340"
5- reg: Address range of the DMAC registers
6- interrupt: Should contain the DMAC interrupt number
7- dma-channels: Number of channels supported by hardware
8- dma-requests: Number of DMA request lines supported, up to 16
9- dma-masters: Number of AHB masters supported by the controller
10- #dma-cells: must be <3>
11- chan_allocation_order: order of allocation of channel, 0 (default): ascending,
12  1: descending
13- chan_priority: priority of channels. 0 (default): increase from chan 0->n, 1:
14  increase from chan n->0
15- block_size: Maximum block size supported by the controller
16- data-width: Maximum data width supported by hardware per AHB master
17  (in bytes, power of 2)
18
19
20Deprecated properties:
21- data_width: Maximum data width supported by hardware per AHB master
22  (0 - 8bits, 1 - 16bits, ..., 5 - 256bits)
23
24
25Optional properties:
26- is_private: The device channels should be marked as private and not for by the
27  general purpose DMA channel allocator. False if not passed.
28- multi-block: Multi block transfers supported by hardware. Array property with
29  one cell per channel. 0: not supported, 1 (default): supported.
30
31Example:
32
33	dmahost: dma@fc000000 {
34		compatible = "snps,dma-spear1340";
35		reg = <0xfc000000 0x1000>;
36		interrupt-parent = <&vic1>;
37		interrupts = <12>;
38
39		dma-channels = <8>;
40		dma-requests = <16>;
41		dma-masters = <2>;
42		#dma-cells = <3>;
43		chan_allocation_order = <1>;
44		chan_priority = <1>;
45		block_size = <0xfff>;
46		data-width = <8 8>;
47	};
48
49DMA clients connected to the Designware DMA controller must use the format
50described in the dma.txt file, using a four-cell specifier for each channel.
51The four cells in order are:
52
531. A phandle pointing to the DMA controller
542. The DMA request line number
553. Memory master for transfers on allocated channel
564. Peripheral master for transfers on allocated channel
57
58Example:
59
60	serial@e0000000 {
61		compatible = "arm,pl011", "arm,primecell";
62		reg = <0xe0000000 0x1000>;
63		interrupts = <0 35 0x4>;
64		dmas = <&dmahost 12 0 1>,
65			<&dmahost 13 1 0>;
66		dma-names = "rx", "rx";
67	};
68