1* Renesas R-Car (RZ/G) DMA Controller Device Tree bindings 2 3Renesas R-Car Generation 2 SoCs have multiple multi-channel DMA 4controller instances named DMAC capable of serving multiple clients. Channels 5can be dedicated to specific clients or shared between a large number of 6clients. 7 8Each DMA client is connected to one dedicated port of the DMAC, identified by 9an 8-bit port number called the MID/RID. A DMA controller can thus serve up to 10256 clients in total. When the number of hardware channels is lower than the 11number of clients to be served, channels must be shared between multiple DMA 12clients. The association of DMA clients to DMAC channels is fully dynamic and 13not described in these device tree bindings. 14 15Required Properties: 16 17- compatible: "renesas,dmac-<soctype>", "renesas,rcar-dmac" as fallback. 18 Examples with soctypes are: 19 - "renesas,dmac-r8a7743" (RZ/G1M) 20 - "renesas,dmac-r8a7745" (RZ/G1E) 21 - "renesas,dmac-r8a77470" (RZ/G1C) 22 - "renesas,dmac-r8a7790" (R-Car H2) 23 - "renesas,dmac-r8a7791" (R-Car M2-W) 24 - "renesas,dmac-r8a7792" (R-Car V2H) 25 - "renesas,dmac-r8a7793" (R-Car M2-N) 26 - "renesas,dmac-r8a7794" (R-Car E2) 27 - "renesas,dmac-r8a7795" (R-Car H3) 28 - "renesas,dmac-r8a7796" (R-Car M3-W) 29 - "renesas,dmac-r8a77965" (R-Car M3-N) 30 - "renesas,dmac-r8a77970" (R-Car V3M) 31 - "renesas,dmac-r8a77980" (R-Car V3H) 32 - "renesas,dmac-r8a77990" (R-Car E3) 33 - "renesas,dmac-r8a77995" (R-Car D3) 34 35- reg: base address and length of the registers block for the DMAC 36 37- interrupts: interrupt specifiers for the DMAC, one for each entry in 38 interrupt-names. 39- interrupt-names: one entry for the error interrupt, named "error", plus one 40 entry per channel, named "ch%u", where %u is the channel number ranging from 41 zero to the number of channels minus one. 42 43- clock-names: "fck" for the functional clock 44- clocks: a list of phandle + clock-specifier pairs, one for each entry 45 in clock-names. 46- clock-names: must contain "fck" for the functional clock. 47 48- #dma-cells: must be <1>, the cell specifies the MID/RID of the DMAC port 49 connected to the DMA client 50- dma-channels: number of DMA channels 51 52Example: R8A7790 (R-Car H2) SYS-DMACs 53 54 dmac0: dma-controller@e6700000 { 55 compatible = "renesas,dmac-r8a7790", "renesas,rcar-dmac"; 56 reg = <0 0xe6700000 0 0x20000>; 57 interrupts = <0 197 IRQ_TYPE_LEVEL_HIGH 58 0 200 IRQ_TYPE_LEVEL_HIGH 59 0 201 IRQ_TYPE_LEVEL_HIGH 60 0 202 IRQ_TYPE_LEVEL_HIGH 61 0 203 IRQ_TYPE_LEVEL_HIGH 62 0 204 IRQ_TYPE_LEVEL_HIGH 63 0 205 IRQ_TYPE_LEVEL_HIGH 64 0 206 IRQ_TYPE_LEVEL_HIGH 65 0 207 IRQ_TYPE_LEVEL_HIGH 66 0 208 IRQ_TYPE_LEVEL_HIGH 67 0 209 IRQ_TYPE_LEVEL_HIGH 68 0 210 IRQ_TYPE_LEVEL_HIGH 69 0 211 IRQ_TYPE_LEVEL_HIGH 70 0 212 IRQ_TYPE_LEVEL_HIGH 71 0 213 IRQ_TYPE_LEVEL_HIGH 72 0 214 IRQ_TYPE_LEVEL_HIGH>; 73 interrupt-names = "error", 74 "ch0", "ch1", "ch2", "ch3", 75 "ch4", "ch5", "ch6", "ch7", 76 "ch8", "ch9", "ch10", "ch11", 77 "ch12", "ch13", "ch14"; 78 clocks = <&mstp2_clks R8A7790_CLK_SYS_DMAC0>; 79 clock-names = "fck"; 80 #dma-cells = <1>; 81 dma-channels = <15>; 82 }; 83 84 dmac1: dma-controller@e6720000 { 85 compatible = "renesas,dmac-r8a7790", "renesas,rcar-dmac"; 86 reg = <0 0xe6720000 0 0x20000>; 87 interrupts = <0 220 IRQ_TYPE_LEVEL_HIGH 88 0 216 IRQ_TYPE_LEVEL_HIGH 89 0 217 IRQ_TYPE_LEVEL_HIGH 90 0 218 IRQ_TYPE_LEVEL_HIGH 91 0 219 IRQ_TYPE_LEVEL_HIGH 92 0 308 IRQ_TYPE_LEVEL_HIGH 93 0 309 IRQ_TYPE_LEVEL_HIGH 94 0 310 IRQ_TYPE_LEVEL_HIGH 95 0 311 IRQ_TYPE_LEVEL_HIGH 96 0 312 IRQ_TYPE_LEVEL_HIGH 97 0 313 IRQ_TYPE_LEVEL_HIGH 98 0 314 IRQ_TYPE_LEVEL_HIGH 99 0 315 IRQ_TYPE_LEVEL_HIGH 100 0 316 IRQ_TYPE_LEVEL_HIGH 101 0 317 IRQ_TYPE_LEVEL_HIGH 102 0 318 IRQ_TYPE_LEVEL_HIGH>; 103 interrupt-names = "error", 104 "ch0", "ch1", "ch2", "ch3", 105 "ch4", "ch5", "ch6", "ch7", 106 "ch8", "ch9", "ch10", "ch11", 107 "ch12", "ch13", "ch14"; 108 clocks = <&mstp2_clks R8A7790_CLK_SYS_DMAC1>; 109 clock-names = "fck"; 110 #dma-cells = <1>; 111 dma-channels = <15>; 112 }; 113
