1Rockchip RK3288 LVDS interface
2================================
3
4Required properties:
5- compatible: matching the soc type, one of
6	- "rockchip,rk3288-lvds";
7
8- reg: physical base address of the controller and length
9	of memory mapped region.
10- clocks: must include clock specifiers corresponding to entries in the
11	clock-names property.
12- clock-names: must contain "pclk_lvds"
13
14- avdd1v0-supply: regulator phandle for 1.0V analog power
15- avdd1v8-supply: regulator phandle for 1.8V analog power
16- avdd3v3-supply: regulator phandle for 3.3V analog power
17
18- rockchip,grf: phandle to the general register files syscon
19- rockchip,output: "rgb", "lvds" or "duallvds", This describes the output interface
20
21Optional properties:
22- pinctrl-names: must contain a "lcdc" entry.
23- pinctrl-0: pin control group to be used for this controller.
24
25Required nodes:
26
27The lvds has two video ports as described by
28	Documentation/devicetree/bindings/media/video-interfaces.txt
29Their connections are modeled using the OF graph bindings specified in
30	Documentation/devicetree/bindings/graph.txt.
31
32- video port 0 for the VOP input, the remote endpoint maybe vopb or vopl
33- video port 1 for either a panel or subsequent encoder
34
35the lvds panel described by
36	Documentation/devicetree/bindings/display/panel/simple-panel.txt
37
38Panel required properties:
39- ports for remote LVDS output
40
41Panel optional properties:
42- data-mapping: should be "vesa-24","jeida-24" or "jeida-18".
43This describes decribed by:
44	Documentation/devicetree/bindings/display/panel/panel-lvds.txt
45
46Example:
47
48lvds_panel: lvds-panel {
49	compatible = "auo,b101ean01";
50	enable-gpios = <&gpio7 21 GPIO_ACTIVE_HIGH>;
51	data-mapping = "jeida-24";
52
53	ports {
54		panel_in_lvds: endpoint {
55			remote-endpoint = <&lvds_out_panel>;
56		};
57	};
58};
59
60For Rockchip RK3288:
61
62	lvds: lvds@ff96c000 {
63		compatible = "rockchip,rk3288-lvds";
64		rockchip,grf = <&grf>;
65		reg = <0xff96c000 0x4000>;
66		clocks = <&cru PCLK_LVDS_PHY>;
67		clock-names = "pclk_lvds";
68		pinctrl-names = "lcdc";
69		pinctrl-0 = <&lcdc_ctl>;
70		avdd1v0-supply = <&vdd10_lcd>;
71		avdd1v8-supply = <&vcc18_lcd>;
72		avdd3v3-supply = <&vcca_33>;
73		rockchip,output = "rgb";
74		ports {
75			#address-cells = <1>;
76			#size-cells = <0>;
77
78			lvds_in: port@0 {
79				reg = <0>;
80
81				lvds_in_vopb: endpoint@0 {
82					reg = <0>;
83					remote-endpoint = <&vopb_out_lvds>;
84				};
85				lvds_in_vopl: endpoint@1 {
86					reg = <1>;
87					remote-endpoint = <&vopl_out_lvds>;
88				};
89			};
90
91			lvds_out: port@1 {
92				reg = <1>;
93
94				lvds_out_panel: endpoint {
95					remote-endpoint = <&panel_in_lvds>;
96				};
97			};
98		};
99	};
100