1Renesas R-Car LVDS Encoder
2==========================
3
4These DT bindings describe the LVDS encoder embedded in the Renesas R-Car
5Gen2, R-Car Gen3 and RZ/G SoCs.
6
7Required properties:
8
9- compatible : Shall contain one of
10  - "renesas,r8a7743-lvds" for R8A7743 (RZ/G1M) compatible LVDS encoders
11  - "renesas,r8a7790-lvds" for R8A7790 (R-Car H2) compatible LVDS encoders
12  - "renesas,r8a7791-lvds" for R8A7791 (R-Car M2-W) compatible LVDS encoders
13  - "renesas,r8a7793-lvds" for R8A7793 (R-Car M2-N) compatible LVDS encoders
14  - "renesas,r8a7795-lvds" for R8A7795 (R-Car H3) compatible LVDS encoders
15  - "renesas,r8a7796-lvds" for R8A7796 (R-Car M3-W) compatible LVDS encoders
16  - "renesas,r8a77970-lvds" for R8A77970 (R-Car V3M) compatible LVDS encoders
17  - "renesas,r8a77995-lvds" for R8A77995 (R-Car D3) compatible LVDS encoders
18
19- reg: Base address and length for the memory-mapped registers
20- clocks: A phandle + clock-specifier pair for the functional clock
21- resets: A phandle + reset specifier for the module reset
22
23Required nodes:
24
25The LVDS encoder has two video ports. Their connections are modelled using the
26OF graph bindings specified in Documentation/devicetree/bindings/graph.txt.
27
28- Video port 0 corresponds to the parallel RGB input
29- Video port 1 corresponds to the LVDS output
30
31Each port shall have a single endpoint.
32
33
34Example:
35
36	lvds0: lvds@feb90000 {
37		compatible = "renesas,r8a7790-lvds";
38		reg = <0 0xfeb90000 0 0x1c>;
39		clocks = <&cpg CPG_MOD 726>;
40		resets = <&cpg 726>;
41
42		ports {
43			#address-cells = <1>;
44			#size-cells = <0>;
45
46			port@0 {
47				reg = <0>;
48				lvds0_in: endpoint {
49					remote-endpoint = <&du_out_lvds0>;
50				};
51			};
52			port@1 {
53				reg = <1>;
54				lvds0_out: endpoint {
55				};
56			};
57		};
58	};
59