1Cadence DSI bridge
2==================
3
4The Cadence DSI bridge is a DPI to DSI bridge supporting up to 4 DSI lanes.
5
6Required properties:
7- compatible: should be set to "cdns,dsi".
8- reg: physical base address and length of the controller's registers.
9- interrupts: interrupt line connected to the DSI bridge.
10- clocks: DSI bridge clocks.
11- clock-names: must contain "dsi_p_clk" and "dsi_sys_clk".
12- phys: phandle link to the MIPI D-PHY controller.
13- phy-names: must contain "dphy".
14- #address-cells: must be set to 1.
15- #size-cells: must be set to 0.
16
17Optional properties:
18- resets: DSI reset lines.
19- reset-names: can contain "dsi_p_rst".
20
21Required subnodes:
22- ports: Ports as described in Documentation/devicetree/bindings/graph.txt.
23  2 ports are available:
24  * port 0: this port is only needed if some of your DSI devices are
25	    controlled through  an external bus like I2C or SPI. Can have at
26	    most 4 endpoints. The endpoint number is directly encoding the
27	    DSI virtual channel used by this device.
28  * port 1: represents the DPI input.
29  Other ports will be added later to support the new kind of inputs.
30
31- one subnode per DSI device connected on the DSI bus. Each DSI device should
32  contain a reg property encoding its virtual channel.
33
34Cadence DPHY
35============
36
37Cadence DPHY block.
38
39Required properties:
40- compatible: should be set to "cdns,dphy".
41- reg: physical base address and length of the DPHY registers.
42- clocks: DPHY reference clocks.
43- clock-names: must contain "psm" and "pll_ref".
44- #phy-cells: must be set to 0.
45
46
47Example:
48	dphy0: dphy@fd0e0000{
49		compatible = "cdns,dphy";
50		reg = <0x0 0xfd0e0000 0x0 0x1000>;
51		clocks = <&psm_clk>, <&pll_ref_clk>;
52		clock-names = "psm", "pll_ref";
53		#phy-cells = <0>;
54	};
55
56	dsi0: dsi@fd0c0000 {
57		compatible = "cdns,dsi";
58		reg = <0x0 0xfd0c0000 0x0 0x1000>;
59		clocks = <&pclk>, <&sysclk>;
60		clock-names = "dsi_p_clk", "dsi_sys_clk";
61		interrupts = <1>;
62		phys = <&dphy0>;
63		phy-names = "dphy";
64		#address-cells = <1>;
65		#size-cells = <0>;
66
67		ports {
68			#address-cells = <1>;
69			#size-cells = <0>;
70
71			port@1 {
72				reg = <1>;
73				dsi0_dpi_input: endpoint {
74					remote-endpoint = <&xxx_dpi_output>;
75				};
76			};
77		};
78
79		panel: dsi-dev@0 {
80			compatible = "<vendor,panel>";
81			reg = <0>;
82		};
83	};
84
85or
86
87	dsi0: dsi@fd0c0000 {
88		compatible = "cdns,dsi";
89		reg = <0x0 0xfd0c0000 0x0 0x1000>;
90		clocks = <&pclk>, <&sysclk>;
91		clock-names = "dsi_p_clk", "dsi_sys_clk";
92		interrupts = <1>;
93		phys = <&dphy1>;
94		phy-names = "dphy";
95		#address-cells = <1>;
96		#size-cells = <0>;
97
98		ports {
99			#address-cells = <1>;
100			#size-cells = <0>;
101
102			port@0 {
103				reg = <0>;
104				#address-cells = <1>;
105				#size-cells = <0>;
106
107				dsi0_output: endpoint@0 {
108					reg = <0>;
109					remote-endpoint = <&dsi_panel_input>;
110				};
111			};
112
113			port@1 {
114				reg = <1>;
115				dsi0_dpi_input: endpoint {
116					remote-endpoint = <&xxx_dpi_output>;
117				};
118			};
119		};
120	};
121
122	i2c@xxx {
123		panel: panel@59 {
124			compatible = "<vendor,panel>";
125			reg = <0x59>;
126
127			port {
128				dsi_panel_input: endpoint {
129					remote-endpoint = <&dsi0_output>;
130				};
131			};
132		};
133	};
134