1* Renesas R9A06G032 SYSCTRL
2
3Required Properties:
4
5  - compatible: Must be:
6    - "renesas,r9a06g032-sysctrl"
7  - reg: Base address and length of the SYSCTRL IO block.
8  - #clock-cells: Must be 1
9  - clocks: References to the parent clocks:
10	- external 40mhz crystal.
11	- external (optional) 32.768khz
12	- external (optional) jtag input
13	- external (optional) RGMII_REFCLK
14  - clock-names: Must be:
15        clock-names = "mclk", "rtc", "jtag", "rgmii_ref_ext";
16
17Examples
18--------
19
20  - SYSCTRL node:
21
22	sysctrl: system-controller@4000c000 {
23		compatible = "renesas,r9a06g032-sysctrl";
24		reg = <0x4000c000 0x1000>;
25		#clock-cells = <1>;
26
27		clocks = <&ext_mclk>, <&ext_rtc_clk>,
28				<&ext_jtag_clk>, <&ext_rgmii_ref>;
29		clock-names = "mclk", "rtc", "jtag", "rgmii_ref_ext";
30	};
31
32  - Other nodes can use the clocks provided by SYSCTRL as in:
33
34	#include <dt-bindings/clock/r9a06g032-sysctrl.h>
35	uart0: serial@40060000 {
36		compatible = "snps,dw-apb-uart";
37		reg = <0x40060000 0x400>;
38		interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
39		reg-shift = <2>;
40		reg-io-width = <4>;
41		clocks = <&sysctrl R9A06G032_CLK_UART0>;
42		clock-names = "baudclk";
43	};
44