1* Renesas CPG DIV6 Clock
2
3The CPG DIV6 clocks are variable factor clocks provided by the Clock Pulse
4Generator (CPG). Their clock input is divided by a configurable factor from 1
5to 64.
6
7Required Properties:
8
9  - compatible: Must be one of the following
10    - "renesas,r8a73a4-div6-clock" for R8A73A4 (R-Mobile APE6) DIV6 clocks
11    - "renesas,r8a7740-div6-clock" for R8A7740 (R-Mobile A1) DIV6 clocks
12    - "renesas,r8a7790-div6-clock" for R8A7790 (R-Car H2) DIV6 clocks
13    - "renesas,r8a7791-div6-clock" for R8A7791 (R-Car M2-W) DIV6 clocks
14    - "renesas,r8a7793-div6-clock" for R8A7793 (R-Car M2-N) DIV6 clocks
15    - "renesas,r8a7794-div6-clock" for R8A7794 (R-Car E2) DIV6 clocks
16    - "renesas,sh73a0-div6-clock" for SH73A0 (SH-Mobile AG5) DIV6 clocks
17    and "renesas,cpg-div6-clock" as a fallback.
18  - reg: Base address and length of the memory resource used by the DIV6 clock
19  - clocks: Reference to the parent clock(s); either one, four, or eight
20    clocks must be specified.  For clocks with multiple parents, invalid
21    settings must be specified as "<0>".
22  - #clock-cells: Must be 0
23
24
25Optional Properties:
26
27  - clock-output-names: The name of the clock as a free-form string
28
29
30Example
31-------
32
33	sdhi2_clk: sdhi2_clk@e615007c {
34		compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock";
35		reg = <0 0xe615007c 0 4>;
36		clocks = <&pll1_div2_clk>, <&cpg_clocks R8A73A4_CLK_PLL2S>,
37			 <0>, <&extal2_clk>;
38		#clock-cells = <0>;
39		clock-output-names = "sdhi2ck";
40	};
41