1Hisilicon Platforms Device Tree Bindings
2----------------------------------------------------
3Hi3660 SoC
4Required root node properties:
5	- compatible = "hisilicon,hi3660";
6
7HiKey960 Board
8Required root node properties:
9	- compatible = "hisilicon,hi3660-hikey960", "hisilicon,hi3660";
10
11Hi3798cv200 SoC
12Required root node properties:
13	- compatible = "hisilicon,hi3798cv200";
14
15Hi3798cv200 Poplar Board
16Required root node properties:
17	- compatible = "hisilicon,hi3798cv200-poplar", "hisilicon,hi3798cv200";
18
19Hi4511 Board
20Required root node properties:
21	- compatible = "hisilicon,hi3620-hi4511";
22
23Hi6220 SoC
24Required root node properties:
25	- compatible = "hisilicon,hi6220";
26
27HiKey Board
28Required root node properties:
29	- compatible = "hisilicon,hi6220-hikey", "hisilicon,hi6220";
30
31HiP01 ca9x2 Board
32Required root node properties:
33	- compatible = "hisilicon,hip01-ca9x2";
34
35HiP04 D01 Board
36Required root node properties:
37	- compatible = "hisilicon,hip04-d01";
38
39HiP05 D02 Board
40Required root node properties:
41	- compatible = "hisilicon,hip05-d02";
42
43HiP06 D03 Board
44Required root node properties:
45	- compatible = "hisilicon,hip06-d03";
46
47HiP07 D05 Board
48Required root node properties:
49	- compatible = "hisilicon,hip07-d05";
50
51Hisilicon system controller
52
53Required properties:
54- compatible : "hisilicon,sysctrl"
55- reg : Register address and size
56
57Optional properties:
58- smp-offset : offset in sysctrl for notifying slave cpu booting
59		cpu 1, reg;
60		cpu 2, reg + 0x4;
61		cpu 3, reg + 0x8;
62		If reg value is not zero, cpun exit wfi and go
63- resume-offset : offset in sysctrl for notifying cpu0 when resume
64- reboot-offset : offset in sysctrl for system reboot
65
66Example:
67
68	/* for Hi3620 */
69	sysctrl: system-controller@fc802000 {
70		compatible = "hisilicon,sysctrl";
71		reg = <0xfc802000 0x1000>;
72		smp-offset = <0x31c>;
73		resume-offset = <0x308>;
74		reboot-offset = <0x4>;
75	};
76
77-----------------------------------------------------------------------
78Hisilicon Hi3798CV200 Peripheral Controller
79
80The Hi3798CV200 Peripheral Controller controls peripherals, queries
81their status, and configures some functions of peripherals.
82
83Required properties:
84- compatible: Should contain "hisilicon,hi3798cv200-perictrl", "syscon"
85  and "simple-mfd".
86- reg: Register address and size of Peripheral Controller.
87- #address-cells: Should be 1.
88- #size-cells: Should be 1.
89
90Examples:
91
92	perictrl: peripheral-controller@8a20000 {
93		compatible = "hisilicon,hi3798cv200-perictrl", "syscon",
94			     "simple-mfd";
95		reg = <0x8a20000 0x1000>;
96		#address-cells = <1>;
97		#size-cells = <1>;
98	};
99
100-----------------------------------------------------------------------
101Hisilicon Hi6220 system controller
102
103Required properties:
104- compatible : "hisilicon,hi6220-sysctrl"
105- reg : Register address and size
106- #clock-cells: should be set to 1, many clock registers are defined
107  under this controller and this property must be present.
108
109Hisilicon designs this controller as one of the system controllers,
110its main functions are the same as Hisilicon system controller, but
111the register offset of some core modules are different.
112
113Example:
114	/*for Hi6220*/
115	sys_ctrl: sys_ctrl@f7030000 {
116		compatible = "hisilicon,hi6220-sysctrl", "syscon";
117		reg = <0x0 0xf7030000 0x0 0x2000>;
118		#clock-cells = <1>;
119	};
120
121
122Hisilicon Hi6220 Power Always ON domain controller
123
124Required properties:
125- compatible : "hisilicon,hi6220-aoctrl"
126- reg : Register address and size
127- #clock-cells: should be set to 1, many clock registers are defined
128  under this controller and this property must be present.
129
130Hisilicon designs this system controller to control the power always
131on domain for mobile platform.
132
133Example:
134	/*for Hi6220*/
135	ao_ctrl: ao_ctrl@f7800000 {
136		compatible = "hisilicon,hi6220-aoctrl", "syscon";
137		reg = <0x0 0xf7800000 0x0 0x2000>;
138		#clock-cells = <1>;
139	};
140
141
142Hisilicon Hi6220 Media domain controller
143
144Required properties:
145- compatible : "hisilicon,hi6220-mediactrl"
146- reg : Register address and size
147- #clock-cells: should be set to 1, many clock registers are defined
148  under this controller and this property must be present.
149
150Hisilicon designs this system controller to control the multimedia
151domain(e.g. codec, G3D ...) for mobile platform.
152
153Example:
154	/*for Hi6220*/
155	media_ctrl: media_ctrl@f4410000 {
156		compatible = "hisilicon,hi6220-mediactrl", "syscon";
157		reg = <0x0 0xf4410000 0x0 0x1000>;
158		#clock-cells = <1>;
159	};
160
161
162Hisilicon Hi6220 Power Management domain controller
163
164Required properties:
165- compatible : "hisilicon,hi6220-pmctrl"
166- reg : Register address and size
167- #clock-cells: should be set to 1, some clock registers are define
168  under this controller and this property must be present.
169
170Hisilicon designs this system controller to control the power management
171domain for mobile platform.
172
173Example:
174	/*for Hi6220*/
175	pm_ctrl: pm_ctrl@f7032000 {
176		compatible = "hisilicon,hi6220-pmctrl", "syscon";
177		reg = <0x0 0xf7032000 0x0 0x1000>;
178		#clock-cells = <1>;
179	};
180
181
182Hisilicon Hi6220 SRAM controller
183
184Required properties:
185- compatible : "hisilicon,hi6220-sramctrl", "syscon"
186- reg : Register address and size
187
188Hisilicon's SoCs use sram for multiple purpose; on Hi6220 there have several
189SRAM banks for power management, modem, security, etc. Further, use "syscon"
190managing the common sram which can be shared by multiple modules.
191
192Example:
193	/*for Hi6220*/
194	sram: sram@fff80000 {
195		compatible = "hisilicon,hi6220-sramctrl", "syscon";
196		reg = <0x0 0xfff80000 0x0 0x12000>;
197	};
198
199-----------------------------------------------------------------------
200Hisilicon HiP01 system controller
201
202Required properties:
203- compatible : "hisilicon,hip01-sysctrl"
204- reg : Register address and size
205
206The HiP01 system controller is mostly compatible with hisilicon
207system controller,but it has some specific control registers for
208HIP01 SoC family, such as slave core boot, and also some same
209registers located at different offset.
210
211Example:
212
213	/* for hip01-ca9x2 */
214	sysctrl: system-controller@10000000 {
215		compatible = "hisilicon,hip01-sysctrl", "hisilicon,sysctrl";
216		reg = <0x10000000 0x1000>;
217		reboot-offset = <0x4>;
218	};
219
220-----------------------------------------------------------------------
221Hisilicon HiP05/HiP06 PCIe-SAS sub system controller
222
223Required properties:
224- compatible : "hisilicon,pcie-sas-subctrl", "syscon";
225- reg : Register address and size
226
227The PCIe-SAS sub system controller is shared by PCIe and SAS controllers in
228HiP05 or HiP06 Soc to implement some basic configurations.
229
230Example:
231	/* for HiP05 PCIe-SAS sub system */
232	pcie_sas: system_controller@b0000000 {
233		compatible = "hisilicon,pcie-sas-subctrl", "syscon";
234		reg = <0xb0000000 0x10000>;
235	};
236
237Hisilicon HiP05/HiP06 PERI sub system controller
238
239Required properties:
240- compatible : "hisilicon,peri-subctrl", "syscon";
241- reg : Register address and size
242
243The PERI sub system controller is shared by peripheral controllers in
244HiP05 or HiP06 Soc to implement some basic configurations. The peripheral
245controllers include mdio, ddr, iic, uart, timer and so on.
246
247Example:
248	/* for HiP05 sub peri system */
249	peri_c_subctrl: syscon@80000000 {
250		compatible = "hisilicon,peri-subctrl", "syscon";
251		reg = <0x0 0x80000000 0x0 0x10000>;
252	};
253
254Hisilicon HiP05/HiP06 DSA sub system controller
255
256Required properties:
257- compatible : "hisilicon,dsa-subctrl", "syscon";
258- reg : Register address and size
259
260The DSA sub system controller is shared by peripheral controllers in
261HiP05 or HiP06 Soc to implement some basic configurations.
262
263Example:
264	/* for HiP05 dsa sub system */
265	pcie_sas: system_controller@a0000000 {
266		compatible = "hisilicon,dsa-subctrl", "syscon";
267		reg = <0xa0000000 0x10000>;
268	};
269
270-----------------------------------------------------------------------
271Hisilicon CPU controller
272
273Required properties:
274- compatible : "hisilicon,cpuctrl"
275- reg : Register address and size
276
277The clock registers and power registers of secondary cores are defined
278in CPU controller, especially in HIX5HD2 SoC.
279
280-----------------------------------------------------------------------
281PCTRL: Peripheral misc control register
282
283Required Properties:
284- compatible: "hisilicon,pctrl"
285- reg: Address and size of pctrl.
286
287Example:
288
289	/* for Hi3620 */
290	pctrl: pctrl@fca09000 {
291		compatible = "hisilicon,pctrl";
292		reg = <0xfca09000 0x1000>;
293	};
294
295-----------------------------------------------------------------------
296Fabric:
297
298Required Properties:
299- compatible: "hisilicon,hip04-fabric";
300- reg: Address and size of Fabric
301
302-----------------------------------------------------------------------
303Bootwrapper boot method (software protocol on SMP):
304
305Required Properties:
306- compatible: "hisilicon,hip04-bootwrapper";
307- boot-method: Address and size of boot method.
308  [0]: bootwrapper physical address
309  [1]: bootwrapper size
310  [2]: relocation physical address
311  [3]: relocation size
312