1System Control and Management Interface (SCMI) Message Protocol
2----------------------------------------------------------
3
4The SCMI is intended to allow agents such as OSPM to manage various functions
5that are provided by the hardware platform it is running on, including power
6and performance functions.
7
8This binding is intended to define the interface the firmware implementing
9the SCMI as described in ARM document number ARM DUI 0922B ("ARM System Control
10and Management Interface Platform Design Document")[0] provide for OSPM in
11the device tree.
12
13Required properties:
14
15The scmi node with the following properties shall be under the /firmware/ node.
16
17- compatible : shall be "arm,scmi"
18- mboxes: List of phandle and mailbox channel specifiers. It should contain
19	  exactly one or two mailboxes, one for transmitting messages("tx")
20	  and another optional for receiving the notifications("rx") if
21	  supported.
22- shmem : List of phandle pointing to the shared memory(SHM) area as per
23	  generic mailbox client binding.
24- #address-cells : should be '1' if the device has sub-nodes, maps to
25	  protocol identifier for a given sub-node.
26- #size-cells : should be '0' as 'reg' property doesn't have any size
27	  associated with it.
28
29Optional properties:
30
31- mbox-names: shall be "tx" or "rx" depending on mboxes entries.
32
33See Documentation/devicetree/bindings/mailbox/mailbox.txt for more details
34about the generic mailbox controller and client driver bindings.
35
36The mailbox is the only permitted method of calling the SCMI firmware.
37Mailbox doorbell is used as a mechanism to alert the presence of a
38messages and/or notification.
39
40Each protocol supported shall have a sub-node with corresponding compatible
41as described in the following sections. If the platform supports dedicated
42communication channel for a particular protocol, the 3 properties namely:
43mboxes, mbox-names and shmem shall be present in the sub-node corresponding
44to that protocol.
45
46Clock/Performance bindings for the clocks/OPPs based on SCMI Message Protocol
47------------------------------------------------------------
48
49This binding uses the common clock binding[1].
50
51Required properties:
52- #clock-cells : Should be 1. Contains the Clock ID value used by SCMI commands.
53
54Power domain bindings for the power domains based on SCMI Message Protocol
55------------------------------------------------------------
56
57This binding for the SCMI power domain providers uses the generic power
58domain binding[2].
59
60Required properties:
61 - #power-domain-cells : Should be 1. Contains the device or the power
62			 domain ID value used by SCMI commands.
63
64Sensor bindings for the sensors based on SCMI Message Protocol
65--------------------------------------------------------------
66SCMI provides an API to access the various sensors on the SoC.
67
68Required properties:
69- #thermal-sensor-cells: should be set to 1. This property follows the
70			 thermal device tree bindings[3].
71
72			 Valid cell values are raw identifiers (Sensor ID)
73			 as used by the firmware. Refer to  platform details
74			 for your implementation for the IDs to use.
75
76SRAM and Shared Memory for SCMI
77-------------------------------
78
79A small area of SRAM is reserved for SCMI communication between application
80processors and SCP.
81
82The properties should follow the generic mmio-sram description found in [4]
83
84Each sub-node represents the reserved area for SCMI.
85
86Required sub-node properties:
87- reg : The base offset and size of the reserved area with the SRAM
88- compatible : should be "arm,scmi-shmem" for Non-secure SRAM based
89	       shared memory
90
91[0] http://infocenter.arm.com/help/topic/com.arm.doc.den0056a/index.html
92[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
93[2] Documentation/devicetree/bindings/power/power_domain.txt
94[3] Documentation/devicetree/bindings/thermal/thermal.txt
95[4] Documentation/devicetree/bindings/sram/sram.txt
96
97Example:
98
99sram@50000000 {
100	compatible = "mmio-sram";
101	reg = <0x0 0x50000000 0x0 0x10000>;
102
103	#address-cells = <1>;
104	#size-cells = <1>;
105	ranges = <0 0x0 0x50000000 0x10000>;
106
107	cpu_scp_lpri: scp-shmem@0 {
108		compatible = "arm,scmi-shmem";
109		reg = <0x0 0x200>;
110	};
111
112	cpu_scp_hpri: scp-shmem@200 {
113		compatible = "arm,scmi-shmem";
114		reg = <0x200 0x200>;
115	};
116};
117
118mailbox@40000000 {
119	....
120	#mbox-cells = <1>;
121	reg = <0x0 0x40000000 0x0 0x10000>;
122};
123
124firmware {
125
126	...
127
128	scmi {
129		compatible = "arm,scmi";
130		mboxes = <&mailbox 0 &mailbox 1>;
131		mbox-names = "tx", "rx";
132		shmem = <&cpu_scp_lpri &cpu_scp_hpri>;
133		#address-cells = <1>;
134		#size-cells = <0>;
135
136		scmi_devpd: protocol@11 {
137			reg = <0x11>;
138			#power-domain-cells = <1>;
139		};
140
141		scmi_dvfs: protocol@13 {
142			reg = <0x13>;
143			#clock-cells = <1>;
144		};
145
146		scmi_clk: protocol@14 {
147			reg = <0x14>;
148			#clock-cells = <1>;
149		};
150
151		scmi_sensors0: protocol@15 {
152			reg = <0x15>;
153			#thermal-sensor-cells = <1>;
154		};
155	};
156};
157
158cpu@0 {
159	...
160	reg = <0 0>;
161	clocks = <&scmi_dvfs 0>;
162};
163
164hdlcd@7ff60000 {
165	...
166	reg = <0 0x7ff60000 0 0x1000>;
167	clocks = <&scmi_clk 4>;
168	power-domains = <&scmi_devpd 1>;
169};
170
171thermal-zones {
172	soc_thermal {
173		polling-delay-passive = <100>;
174		polling-delay = <1000>;
175					/* sensor ID */
176		thermal-sensors = <&scmi_sensors0 3>;
177		...
178	};
179};
180