1				PCI TEST
2		    Kishon Vijay Abraham I <kishon@ti.com>
3
4Traditionally PCI RC has always been validated by using standard
5PCI cards like ethernet PCI cards or USB PCI cards or SATA PCI cards.
6However with the addition of EP-core in linux kernel, it is possible
7to configure a PCI controller that can operate in EP mode to work as
8a test device.
9
10The PCI endpoint test device is a virtual device (defined in software)
11used to test the endpoint functionality and serve as a sample driver
12for other PCI endpoint devices (to use the EP framework).
13
14The PCI endpoint test device has the following registers:
15
16	1) PCI_ENDPOINT_TEST_MAGIC
17	2) PCI_ENDPOINT_TEST_COMMAND
18	3) PCI_ENDPOINT_TEST_STATUS
19	4) PCI_ENDPOINT_TEST_SRC_ADDR
20	5) PCI_ENDPOINT_TEST_DST_ADDR
21	6) PCI_ENDPOINT_TEST_SIZE
22	7) PCI_ENDPOINT_TEST_CHECKSUM
23	8) PCI_ENDPOINT_TEST_IRQ_TYPE
24	9) PCI_ENDPOINT_TEST_IRQ_NUMBER
25
26*) PCI_ENDPOINT_TEST_MAGIC
27
28This register will be used to test BAR0. A known pattern will be written
29and read back from MAGIC register to verify BAR0.
30
31*) PCI_ENDPOINT_TEST_COMMAND:
32
33This register will be used by the host driver to indicate the function
34that the endpoint device must perform.
35
36Bitfield Description:
37  Bit 0		: raise legacy IRQ
38  Bit 1		: raise MSI IRQ
39  Bit 2		: raise MSI-X IRQ
40  Bit 3		: read command (read data from RC buffer)
41  Bit 4		: write command (write data to RC buffer)
42  Bit 5		: copy command (copy data from one RC buffer to another
43		  RC buffer)
44
45*) PCI_ENDPOINT_TEST_STATUS
46
47This register reflects the status of the PCI endpoint device.
48
49Bitfield Description:
50  Bit 0		: read success
51  Bit 1		: read fail
52  Bit 2		: write success
53  Bit 3		: write fail
54  Bit 4		: copy success
55  Bit 5		: copy fail
56  Bit 6		: IRQ raised
57  Bit 7		: source address is invalid
58  Bit 8		: destination address is invalid
59
60*) PCI_ENDPOINT_TEST_SRC_ADDR
61
62This register contains the source address (RC buffer address) for the
63COPY/READ command.
64
65*) PCI_ENDPOINT_TEST_DST_ADDR
66
67This register contains the destination address (RC buffer address) for
68the COPY/WRITE command.
69
70*) PCI_ENDPOINT_TEST_IRQ_TYPE
71
72This register contains the interrupt type (Legacy/MSI) triggered
73for the READ/WRITE/COPY and raise IRQ (Legacy/MSI) commands.
74
75Possible types:
76 - Legacy	: 0
77 - MSI		: 1
78 - MSI-X	: 2
79
80*) PCI_ENDPOINT_TEST_IRQ_NUMBER
81
82This register contains the triggered ID interrupt.
83
84Admissible values:
85 - Legacy	: 0
86 - MSI		: [1 .. 32]
87 - MSI-X	: [1 .. 2048]
88