Searched refs:UTMIPLL_HW_PWRDN_CFG0 (Results 1 – 2 of 2) sorted by relevance
197 #define UTMIPLL_HW_PWRDN_CFG0 0x52c macro2779 reg = readl_relaxed(clk_base + UTMIPLL_HW_PWRDN_CFG0); in tegra210_put_utmipll_in_iddq()2787 writel_relaxed(reg, clk_base + UTMIPLL_HW_PWRDN_CFG0); in tegra210_put_utmipll_in_iddq()2795 reg = readl_relaxed(clk_base + UTMIPLL_HW_PWRDN_CFG0); in tegra210_put_utmipll_out_iddq()2797 writel_relaxed(reg, clk_base + UTMIPLL_HW_PWRDN_CFG0); in tegra210_put_utmipll_out_iddq()2817 reg = readl_relaxed(clk_base + UTMIPLL_HW_PWRDN_CFG0); in tegra210_utmi_param_configure()2819 writel_relaxed(reg, clk_base + UTMIPLL_HW_PWRDN_CFG0); in tegra210_utmi_param_configure()2873 reg = readl_relaxed(clk_base + UTMIPLL_HW_PWRDN_CFG0); in tegra210_utmi_param_configure()2876 writel_relaxed(reg, clk_base + UTMIPLL_HW_PWRDN_CFG0); in tegra210_utmi_param_configure()2887 reg = readl_relaxed(clk_base + UTMIPLL_HW_PWRDN_CFG0); in tegra210_utmi_param_configure()[all …]
205 #define UTMIPLL_HW_PWRDN_CFG0 0x52c macro1811 value = readl_relaxed(pll->clk_base + UTMIPLL_HW_PWRDN_CFG0); in clk_pllu_tegra114_enable()1815 writel_relaxed(value, pll->clk_base + UTMIPLL_HW_PWRDN_CFG0); in clk_pllu_tegra114_enable()1828 value = readl_relaxed(pll->clk_base + UTMIPLL_HW_PWRDN_CFG0); in clk_pllu_tegra114_enable()1831 writel_relaxed(value, pll->clk_base + UTMIPLL_HW_PWRDN_CFG0); in clk_pllu_tegra114_enable()1836 value = readl_relaxed(pll->clk_base + UTMIPLL_HW_PWRDN_CFG0); in clk_pllu_tegra114_enable()1838 writel_relaxed(value, pll->clk_base + UTMIPLL_HW_PWRDN_CFG0); in clk_pllu_tegra114_enable()
