Lines Matching refs:UTMIPLL_HW_PWRDN_CFG0
197 #define UTMIPLL_HW_PWRDN_CFG0 0x52c macro
2779 reg = readl_relaxed(clk_base + UTMIPLL_HW_PWRDN_CFG0); in tegra210_put_utmipll_in_iddq()
2787 writel_relaxed(reg, clk_base + UTMIPLL_HW_PWRDN_CFG0); in tegra210_put_utmipll_in_iddq()
2795 reg = readl_relaxed(clk_base + UTMIPLL_HW_PWRDN_CFG0); in tegra210_put_utmipll_out_iddq()
2797 writel_relaxed(reg, clk_base + UTMIPLL_HW_PWRDN_CFG0); in tegra210_put_utmipll_out_iddq()
2817 reg = readl_relaxed(clk_base + UTMIPLL_HW_PWRDN_CFG0); in tegra210_utmi_param_configure()
2819 writel_relaxed(reg, clk_base + UTMIPLL_HW_PWRDN_CFG0); in tegra210_utmi_param_configure()
2873 reg = readl_relaxed(clk_base + UTMIPLL_HW_PWRDN_CFG0); in tegra210_utmi_param_configure()
2876 writel_relaxed(reg, clk_base + UTMIPLL_HW_PWRDN_CFG0); in tegra210_utmi_param_configure()
2887 reg = readl_relaxed(clk_base + UTMIPLL_HW_PWRDN_CFG0); in tegra210_utmi_param_configure()
2889 writel_relaxed(reg, clk_base + UTMIPLL_HW_PWRDN_CFG0); in tegra210_utmi_param_configure()
2986 reg = readl_relaxed(clk_base + UTMIPLL_HW_PWRDN_CFG0); in tegra210_init_pllu()