| /Linux-v6.1/drivers/gpu/drm/i915/display/ |
| D | intel_crtc_state_dump.c | 26 intel_dump_m_n_config(const struct intel_crtc_state *pipe_config, in intel_dump_m_n_config() argument
30 struct drm_i915_private *i915 = to_i915(pipe_config->uapi.crtc->dev); in intel_dump_m_n_config()
146 void intel_crtc_state_dump(const struct intel_crtc_state *pipe_config, in intel_crtc_state_dump() argument
150 struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc); in intel_crtc_state_dump()
159 str_yes_no(pipe_config->hw.enable), context); in intel_crtc_state_dump()
161 if (!pipe_config->hw.enable) in intel_crtc_state_dump()
164 snprintf_output_types(buf, sizeof(buf), pipe_config->output_types); in intel_crtc_state_dump()
167 str_yes_no(pipe_config->hw.active), in intel_crtc_state_dump()
168 buf, pipe_config->output_types, in intel_crtc_state_dump()
169 output_formats(pipe_config->output_format)); in intel_crtc_state_dump()
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| D | g4x_hdmi.c | 82 struct intel_crtc_state *pipe_config) in intel_hdmi_get_config() argument
90 pipe_config->output_types |= BIT(INTEL_OUTPUT_HDMI); in intel_hdmi_get_config()
105 pipe_config->has_hdmi_sink = true; in intel_hdmi_get_config()
107 pipe_config->infoframes.enable |= in intel_hdmi_get_config()
108 intel_hdmi_infoframes_enabled(encoder, pipe_config); in intel_hdmi_get_config()
110 if (pipe_config->infoframes.enable) in intel_hdmi_get_config()
111 pipe_config->has_infoframe = true; in intel_hdmi_get_config()
114 pipe_config->has_audio = true; in intel_hdmi_get_config()
118 pipe_config->limited_color_range = true; in intel_hdmi_get_config()
120 pipe_config->hw.adjusted_mode.flags |= flags; in intel_hdmi_get_config()
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| D | intel_modeset_verify.c | 88 const struct intel_crtc_state *pipe_config) in intel_pipe_config_sanity_check() argument
90 if (pipe_config->has_pch_encoder) { in intel_pipe_config_sanity_check()
91 int fdi_dotclock = intel_dotclock_calculate(intel_fdi_link_freq(dev_priv, pipe_config), in intel_pipe_config_sanity_check()
92 &pipe_config->fdi_m_n); in intel_pipe_config_sanity_check()
93 int dotclock = pipe_config->hw.adjusted_mode.crtc_clock; in intel_pipe_config_sanity_check()
164 struct intel_crtc_state *pipe_config = old_crtc_state; in verify_crtc_state() local
176 pipe_config->hw.enable = new_crtc_state->hw.enable; in verify_crtc_state()
178 intel_crtc_get_pipe_config(pipe_config); in verify_crtc_state()
181 if (IS_I830(dev_priv) && pipe_config->hw.active) in verify_crtc_state()
182 pipe_config->hw.active = new_crtc_state->hw.active; in verify_crtc_state()
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| D | g4x_dp.c | 55 struct intel_crtc_state *pipe_config) in g4x_dp_set_clock() argument
77 if (pipe_config->port_clock == divisor[i].dot) { in g4x_dp_set_clock()
78 pipe_config->dpll = divisor[i]; in g4x_dp_set_clock()
79 pipe_config->clock_set = true; in g4x_dp_set_clock()
87 const struct intel_crtc_state *pipe_config) in intel_dp_prepare() argument
92 struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc); in intel_dp_prepare()
93 const struct drm_display_mode *adjusted_mode = &pipe_config->hw.adjusted_mode; in intel_dp_prepare()
96 pipe_config->port_clock, in intel_dp_prepare()
97 pipe_config->lane_count); in intel_dp_prepare()
122 intel_dp->DP |= DP_PORT_WIDTH(pipe_config->lane_count); in intel_dp_prepare()
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| D | intel_dp_mst.c | 132 struct intel_crtc_state *pipe_config, in intel_dp_mst_compute_config() argument
143 &pipe_config->hw.adjusted_mode; in intel_dp_mst_compute_config()
150 pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB; in intel_dp_mst_compute_config()
151 pipe_config->has_pch_encoder = false; in intel_dp_mst_compute_config()
154 pipe_config->has_audio = connector->port->has_audio; in intel_dp_mst_compute_config()
156 pipe_config->has_audio = in intel_dp_mst_compute_config()
169 limits.min_bpp = intel_dp_min_bpp(pipe_config->output_format); in intel_dp_mst_compute_config()
178 limits.max_bpp = min(pipe_config->pipe_bpp, 24); in intel_dp_mst_compute_config()
180 intel_dp_adjust_compliance_config(intel_dp, pipe_config, &limits); in intel_dp_mst_compute_config()
182 ret = intel_dp_mst_compute_link_config(encoder, pipe_config, in intel_dp_mst_compute_config()
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| D | intel_lvds.c | 123 struct intel_crtc_state *pipe_config) in intel_lvds_get_config() argument
129 pipe_config->output_types |= BIT(INTEL_OUTPUT_LVDS); in intel_lvds_get_config()
141 pipe_config->hw.adjusted_mode.flags |= flags; in intel_lvds_get_config()
144 pipe_config->gmch_pfit.lvds_border_bits = in intel_lvds_get_config()
151 pipe_config->gmch_pfit.control |= tmp & PANEL_8TO6_DITHER_ENABLE; in intel_lvds_get_config()
154 pipe_config->hw.adjusted_mode.crtc_clock = pipe_config->port_clock; in intel_lvds_get_config()
229 const struct intel_crtc_state *pipe_config, in intel_pre_enable_lvds() argument
234 struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc); in intel_pre_enable_lvds()
235 const struct drm_display_mode *adjusted_mode = &pipe_config->hw.adjusted_mode; in intel_pre_enable_lvds()
242 pipe_config->shared_dpll); in intel_pre_enable_lvds()
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| D | intel_dp.c | 1149 const struct intel_crtc_state *pipe_config) in intel_dp_source_supports_fec() argument
1157 if (DISPLAY_VER(dev_priv) == 11 && pipe_config->cpu_transcoder != TRANSCODER_A) in intel_dp_source_supports_fec()
1164 const struct intel_crtc_state *pipe_config) in intel_dp_supports_fec() argument
1166 return intel_dp_source_supports_fec(intel_dp, pipe_config) && in intel_dp_supports_fec()
1264 struct intel_crtc_state *pipe_config, in intel_dp_adjust_compliance_config() argument
1274 pipe_config->dither_force_disable = bpp == 6 * 3; in intel_dp_adjust_compliance_config()
1328 struct intel_crtc_state *pipe_config, in intel_dp_compute_link_config_wide() argument
1332 int bpp, i, lane_count, clock = intel_dp_mode_clock(pipe_config, conn_state); in intel_dp_compute_link_config_wide()
1336 int output_bpp = intel_dp_output_bpp(pipe_config->output_format, bpp); in intel_dp_compute_link_config_wide()
1353 pipe_config->lane_count = lane_count; in intel_dp_compute_link_config_wide()
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| D | intel_crt.c | 136 struct intel_crtc_state *pipe_config) in intel_crt_get_config() argument
138 pipe_config->output_types |= BIT(INTEL_OUTPUT_ANALOG); in intel_crt_get_config()
140 pipe_config->hw.adjusted_mode.flags |= intel_crt_get_flags(encoder); in intel_crt_get_config()
142 pipe_config->hw.adjusted_mode.crtc_clock = pipe_config->port_clock; in intel_crt_get_config()
146 struct intel_crtc_state *pipe_config) in hsw_crt_get_config() argument
148 lpt_pch_get_config(pipe_config); in hsw_crt_get_config()
150 hsw_ddi_get_config(encoder, pipe_config); in hsw_crt_get_config()
152 pipe_config->hw.adjusted_mode.flags &= ~(DRM_MODE_FLAG_PHSYNC | in hsw_crt_get_config()
156 pipe_config->hw.adjusted_mode.flags |= intel_crt_get_flags(encoder); in hsw_crt_get_config()
385 struct intel_crtc_state *pipe_config, in intel_crt_compute_config() argument
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| D | intel_dvo.c | 164 struct intel_crtc_state *pipe_config) in intel_dvo_get_config() argument
170 pipe_config->output_types |= BIT(INTEL_OUTPUT_DVO); in intel_dvo_get_config()
182 pipe_config->hw.adjusted_mode.flags |= flags; in intel_dvo_get_config()
184 pipe_config->hw.adjusted_mode.crtc_clock = pipe_config->port_clock; in intel_dvo_get_config()
204 const struct intel_crtc_state *pipe_config, in intel_enable_dvo() argument
213 &pipe_config->hw.mode, in intel_enable_dvo()
214 &pipe_config->hw.adjusted_mode); in intel_enable_dvo()
255 struct intel_crtc_state *pipe_config, in intel_dvo_compute_config() argument
260 struct drm_display_mode *adjusted_mode = &pipe_config->hw.adjusted_mode; in intel_dvo_compute_config()
281 pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB; in intel_dvo_compute_config()
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| D | intel_display.c | 2944 struct intel_crtc_state *pipe_config) in intel_get_transcoder_timings() argument
2948 enum transcoder cpu_transcoder = pipe_config->cpu_transcoder; in intel_get_transcoder_timings()
2952 pipe_config->hw.adjusted_mode.crtc_hdisplay = (tmp & 0xffff) + 1; in intel_get_transcoder_timings()
2953 pipe_config->hw.adjusted_mode.crtc_htotal = ((tmp >> 16) & 0xffff) + 1; in intel_get_transcoder_timings()
2957 pipe_config->hw.adjusted_mode.crtc_hblank_start = in intel_get_transcoder_timings()
2959 pipe_config->hw.adjusted_mode.crtc_hblank_end = in intel_get_transcoder_timings()
2963 pipe_config->hw.adjusted_mode.crtc_hsync_start = (tmp & 0xffff) + 1; in intel_get_transcoder_timings()
2964 pipe_config->hw.adjusted_mode.crtc_hsync_end = ((tmp >> 16) & 0xffff) + 1; in intel_get_transcoder_timings()
2967 pipe_config->hw.adjusted_mode.crtc_vdisplay = (tmp & 0xffff) + 1; in intel_get_transcoder_timings()
2968 pipe_config->hw.adjusted_mode.crtc_vtotal = ((tmp >> 16) & 0xffff) + 1; in intel_get_transcoder_timings()
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| D | intel_fdi.c | 129 struct intel_crtc_state *pipe_config) in ilk_check_fdi_lanes() argument
132 struct drm_atomic_state *state = pipe_config->uapi.state; in ilk_check_fdi_lanes()
138 pipe_name(pipe), pipe_config->fdi_lanes); in ilk_check_fdi_lanes()
139 if (pipe_config->fdi_lanes > 4) { in ilk_check_fdi_lanes()
142 pipe_name(pipe), pipe_config->fdi_lanes); in ilk_check_fdi_lanes()
147 if (pipe_config->fdi_lanes > 2) { in ilk_check_fdi_lanes()
150 pipe_config->fdi_lanes); in ilk_check_fdi_lanes()
165 if (pipe_config->fdi_lanes <= 2) in ilk_check_fdi_lanes()
177 pipe_name(pipe), pipe_config->fdi_lanes); in ilk_check_fdi_lanes()
182 if (pipe_config->fdi_lanes > 2) { in ilk_check_fdi_lanes()
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| D | vlv_dsi.c | 271 struct intel_crtc_state *pipe_config, in intel_dsi_compute_config() argument
278 struct drm_display_mode *adjusted_mode = &pipe_config->hw.adjusted_mode; in intel_dsi_compute_config()
282 pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB; in intel_dsi_compute_config()
288 ret = intel_panel_fitting(pipe_config, conn_state); in intel_dsi_compute_config()
299 pipe_config->pipe_bpp = 24; in intel_dsi_compute_config()
301 pipe_config->pipe_bpp = 18; in intel_dsi_compute_config()
305 pipe_config->mode_flags |= in intel_dsi_compute_config()
310 pipe_config->cpu_transcoder = TRANSCODER_DSI_C; in intel_dsi_compute_config()
312 pipe_config->cpu_transcoder = TRANSCODER_DSI_A; in intel_dsi_compute_config()
314 ret = bxt_dsi_pll_compute(encoder, pipe_config); in intel_dsi_compute_config()
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| D | icl_dsi.c | 298 const struct intel_crtc_state *pipe_config) in configure_dual_link_mode() argument
311 &pipe_config->hw.adjusted_mode; in configure_dual_link_mode()
718 const struct intel_crtc_state *pipe_config) in gen11_dsi_configure_transcoder() argument
722 struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc); in gen11_dsi_configure_transcoder()
738 if (afe_clk(encoder, pipe_config) >= 1500 * 1000) { in gen11_dsi_configure_transcoder()
764 if (pipe_config->dsc.compression_enable) { in gen11_dsi_configure_transcoder()
834 configure_dual_link_mode(encoder, pipe_config); in gen11_dsi_configure_transcoder()
1224 const struct intel_crtc_state *pipe_config, in gen11_dsi_pre_enable() argument
1228 gen11_dsi_map_pll(encoder, pipe_config); in gen11_dsi_pre_enable()
1231 gen11_dsi_enable_port_and_phy(encoder, pipe_config); in gen11_dsi_pre_enable()
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| D | intel_ddi.c | 328 static void ddi_dotclock_get(struct intel_crtc_state *pipe_config) in ddi_dotclock_get() argument
331 if (pipe_config->has_pch_encoder) in ddi_dotclock_get()
334 pipe_config->hw.adjusted_mode.crtc_clock = in ddi_dotclock_get()
335 intel_crtc_dotclock(pipe_config); in ddi_dotclock_get()
2210 struct intel_crtc_state *pipe_config) in intel_ddi_mso_get_config() argument
2212 struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc); in intel_ddi_mso_get_config()
2222 pipe_config->splitter.enable = dss1 & SPLITTER_ENABLE; in intel_ddi_mso_get_config()
2223 if (!pipe_config->splitter.enable) in intel_ddi_mso_get_config()
2227 pipe_config->splitter.enable = false; in intel_ddi_mso_get_config()
2237 pipe_config->splitter.link_count = 2; in intel_ddi_mso_get_config()
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| D | intel_pipe_crc.c | 291 struct intel_crtc_state *pipe_config; in intel_crtc_crc_setup_workarounds() local
307 pipe_config = intel_atomic_get_crtc_state(state, crtc); in intel_crtc_crc_setup_workarounds()
308 if (IS_ERR(pipe_config)) { in intel_crtc_crc_setup_workarounds()
309 ret = PTR_ERR(pipe_config); in intel_crtc_crc_setup_workarounds()
313 pipe_config->uapi.mode_changed = pipe_config->has_psr; in intel_crtc_crc_setup_workarounds()
314 pipe_config->crc_enabled = enable; in intel_crtc_crc_setup_workarounds()
317 pipe_config->hw.active && crtc->pipe == PIPE_A && in intel_crtc_crc_setup_workarounds()
318 pipe_config->cpu_transcoder == TRANSCODER_EDP) in intel_crtc_crc_setup_workarounds()
319 pipe_config->uapi.mode_changed = true; in intel_crtc_crc_setup_workarounds()
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| D | intel_tv.c | 922 const struct intel_crtc_state *pipe_config, in intel_enable_tv() argument
929 intel_crtc_wait_for_next_vblank(to_intel_crtc(pipe_config->uapi.crtc)); in intel_enable_tv()
1086 struct intel_crtc_state *pipe_config) in intel_tv_get_config() argument
1090 &pipe_config->hw.adjusted_mode; in intel_tv_get_config()
1098 pipe_config->output_types |= BIT(INTEL_OUTPUT_TVOUT); in intel_tv_get_config()
1120 tv_mode.clock = pipe_config->port_clock; in intel_tv_get_config()
1147 intel_tv_mode_to_mode(&mode, &tv_mode, pipe_config->port_clock); in intel_tv_get_config()
1163 pipe_config->mode_flags |= in intel_tv_get_config()
1185 struct intel_crtc_state *pipe_config, in intel_tv_compute_config() argument
1189 to_intel_atomic_state(pipe_config->uapi.state); in intel_tv_compute_config()
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| D | intel_sdvo.c | 1251 static void i9xx_adjust_sdvo_tv_clock(struct intel_crtc_state *pipe_config) in i9xx_adjust_sdvo_tv_clock() argument
1253 struct drm_i915_private *dev_priv = to_i915(pipe_config->uapi.crtc->dev); in i9xx_adjust_sdvo_tv_clock()
1254 unsigned dotclock = pipe_config->port_clock; in i9xx_adjust_sdvo_tv_clock()
1255 struct dpll *clock = &pipe_config->dpll; in i9xx_adjust_sdvo_tv_clock()
1278 pipe_config->clock_set = true; in i9xx_adjust_sdvo_tv_clock()
1301 struct intel_crtc_state *pipe_config, in intel_sdvo_compute_config() argument
1309 struct drm_display_mode *adjusted_mode = &pipe_config->hw.adjusted_mode; in intel_sdvo_compute_config()
1310 struct drm_display_mode *mode = &pipe_config->hw.mode; in intel_sdvo_compute_config()
1313 pipe_config->pipe_bpp = 8*3; in intel_sdvo_compute_config()
1314 pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB; in intel_sdvo_compute_config()
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| D | intel_hdmi.c | 254 const struct intel_crtc_state *pipe_config) in g4x_infoframes_enabled() argument
330 const struct intel_crtc_state *pipe_config) in ibx_infoframes_enabled() argument
333 enum pipe pipe = to_intel_crtc(pipe_config->uapi.crtc)->pipe; in ibx_infoframes_enabled()
412 const struct intel_crtc_state *pipe_config) in cpt_infoframes_enabled() argument
415 enum pipe pipe = to_intel_crtc(pipe_config->uapi.crtc)->pipe; in cpt_infoframes_enabled()
489 const struct intel_crtc_state *pipe_config) in vlv_infoframes_enabled() argument
492 enum pipe pipe = to_intel_crtc(pipe_config->uapi.crtc)->pipe; in vlv_infoframes_enabled()
563 const struct intel_crtc_state *pipe_config) in hsw_infoframes_enabled() argument
567 HSW_TVIDEO_DIP_CTL(pipe_config->cpu_transcoder)); in hsw_infoframes_enabled()
2237 struct intel_crtc_state *pipe_config, in intel_hdmi_compute_config() argument
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| D | intel_lspcon.h | 35 const struct intel_crtc_state *pipe_config);
37 const struct intel_crtc_state *pipe_config);
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| D | intel_fdi.h | 16 const struct intel_crtc_state *pipe_config);
18 struct intel_crtc_state *pipe_config);
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| D | intel_dp.h | 34 struct intel_crtc_state *pipe_config,
57 struct intel_crtc_state *pipe_config,
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| D | intel_vdsc.c | 452 int intel_dsc_compute_params(struct intel_crtc_state *pipe_config) in intel_dsc_compute_params() argument
454 struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc); in intel_dsc_compute_params()
456 struct drm_dsc_config *vdsc_cfg = &pipe_config->dsc.config; in intel_dsc_compute_params()
457 u16 compressed_bpp = pipe_config->dsc.compressed_bpp; in intel_dsc_compute_params()
462 vdsc_cfg->pic_width = pipe_config->hw.adjusted_mode.crtc_hdisplay; in intel_dsc_compute_params()
464 pipe_config->dsc.slice_count); in intel_dsc_compute_params()
473 vdsc_cfg->bits_per_component = pipe_config->pipe_bpp / 3; in intel_dsc_compute_params()
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| D | g4x_dp.h | 23 struct intel_crtc_state *pipe_config);
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| /Linux-v6.1/drivers/gpu/drm/amd/display/dc/ |
| D | dc_dmub_srv.c | 466 pipe_data->pipe_config.vblank_data.drr_info.drr_in_use = true; in populate_subvp_cmd_drr_info()
467 pipe_data->pipe_config.vblank_data.drr_info.use_ramping = false; // for now don't use ramping in populate_subvp_cmd_drr_info()
468 …pipe_data->pipe_config.vblank_data.drr_info.drr_window_size_ms = 4; // hardcode 4ms DRR window for… in populate_subvp_cmd_drr_info()
491 pipe_data->pipe_config.vblank_data.drr_info.min_vtotal_supported = min_vtotal_supported; in populate_subvp_cmd_drr_info()
492 pipe_data->pipe_config.vblank_data.drr_info.max_vtotal_supported = max_vtotal_supported; in populate_subvp_cmd_drr_info()
539 pipe_data->pipe_config.vblank_data.pix_clk_100hz = vblank_pipe->stream->timing.pix_clk_100hz; in populate_subvp_cmd_vblank_pipe_info()
540 pipe_data->pipe_config.vblank_data.vblank_start = vblank_pipe->stream->timing.v_total - in populate_subvp_cmd_vblank_pipe_info()
542 pipe_data->pipe_config.vblank_data.vtotal = vblank_pipe->stream->timing.v_total; in populate_subvp_cmd_vblank_pipe_info()
543 pipe_data->pipe_config.vblank_data.htotal = vblank_pipe->stream->timing.h_total; in populate_subvp_cmd_vblank_pipe_info()
544 pipe_data->pipe_config.vblank_data.vblank_pipe_index = vblank_pipe->pipe_idx; in populate_subvp_cmd_vblank_pipe_info()
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| /Linux-v6.1/drivers/usb/renesas_usbhs/ |
| D | pipe.c | 477 struct renesas_usbhs_driver_pipe_config *pipe_config = in usbhsp_setup_pipebuff() local
489 buff_size = pipe_config->bufsize; in usbhsp_setup_pipebuff()
490 bufnmb = pipe_config->bufnum; in usbhsp_setup_pipebuff()
507 struct renesas_usbhs_driver_pipe_config *pipe_config = in usbhs_pipe_config_update() local
509 u16 dblb = pipe_config->double_buf ? DBLB : 0; in usbhs_pipe_config_update()
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