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Searched refs:CLK_TOP_UNIVPLL1_D2 (Results 1 – 22 of 22) sorted by relevance

/Linux-v6.1/arch/arm/boot/dts/
Dmt7629.dtsi101 assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL1_D2>;
325 <&topckgen CLK_TOP_UNIVPLL1_D2>;
393 <&topckgen CLK_TOP_UNIVPLL1_D2>;
469 assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL1_D2>,
/Linux-v6.1/include/dt-bindings/clock/
Dmt8135-clk.h43 #define CLK_TOP_UNIVPLL1_D2 32 macro
Dmt7629-clk.h50 #define CLK_TOP_UNIVPLL1_D2 40 macro
Dmt7622-clk.h44 #define CLK_TOP_UNIVPLL1_D2 32 macro
Dmt6797-clk.h68 #define CLK_TOP_UNIVPLL1_D2 58 macro
Dmediatek,mt6795-clk.h71 #define CLK_TOP_UNIVPLL1_D2 60 macro
Dmt6765-clk.h58 #define CLK_TOP_UNIVPLL1_D2 23 macro
Dmt8173-clk.h73 #define CLK_TOP_UNIVPLL1_D2 63 macro
Dmediatek,mt8365-clk.h33 #define CLK_TOP_UNIVPLL1_D2 23 macro
Dmt2712-clk.h57 #define CLK_TOP_UNIVPLL1_D2 26 macro
Dmt2701-clk.h36 #define CLK_TOP_UNIVPLL1_D2 26 macro
/Linux-v6.1/drivers/clk/mediatek/
Dclk-mt6795-topckgen.c427 FACTOR(CLK_TOP_UNIVPLL1_D2, "univpll1_d2", "univ_624m", 1, 2),
Dclk-mt8135.c62 FACTOR(CLK_TOP_UNIVPLL1_D2, "univpll1_d2", "univpll_624m", 1, 2),
Dclk-mt7629.c419 FACTOR(CLK_TOP_UNIVPLL1_D2, "univpll1_d2", "univpll", 1, 4),
Dclk-mt6797.c50 FACTOR(CLK_TOP_UNIVPLL1_D2, "univpll1_d2", "univpll_d2", 1, 2),
Dclk-mt7622.c411 FACTOR(CLK_TOP_UNIVPLL1_D2, "univpll1_d2", "univpll", 1, 4),
Dclk-mt2701.c85 FACTOR(CLK_TOP_UNIVPLL1_D2, "univpll1_d2", "univpll_d2", 1, 2),
Dclk-mt2712.c99 FACTOR(CLK_TOP_UNIVPLL1_D2, "univpll1_d2", "univpll_d2", 1,
Dclk-mt6765.c108 FACTOR(CLK_TOP_UNIVPLL1_D2, "univpll1_d2", "univpll_d2", 1, 2),
Dclk-mt8365.c52 FACTOR(CLK_TOP_UNIVPLL1_D2, "univpll1_d2", "univpll", 1, 4),
Dclk-mt8173.c109 FACTOR(CLK_TOP_UNIVPLL1_D2, "univpll1_d2", "univ_624m", 1, 2),
/Linux-v6.1/arch/arm64/boot/dts/mediatek/
Dmt2712e.dtsi322 assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL1_D2>;