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Searched refs:CLK_TOP_AXI_SEL (Results 1 – 24 of 24) sorted by relevance

/Linux-v6.1/include/dt-bindings/clock/
Dmt8135-clk.h73 #define CLK_TOP_AXI_SEL 62 macro
Dmt7629-clk.h83 #define CLK_TOP_AXI_SEL 73 macro
Dmt7622-clk.h68 #define CLK_TOP_AXI_SEL 56 macro
Dmediatek,mt6795-clk.h90 #define CLK_TOP_AXI_SEL 79 macro
Dmt6765-clk.h131 #define CLK_TOP_AXI_SEL 96 macro
Dmt8173-clk.h92 #define CLK_TOP_AXI_SEL 82 macro
Dmediatek,mt8365-clk.h71 #define CLK_TOP_AXI_SEL 61 macro
Dmt2712-clk.h130 #define CLK_TOP_AXI_SEL 99 macro
Dmt2701-clk.h90 #define CLK_TOP_AXI_SEL 79 macro
Dmt8192-clk.h12 #define CLK_TOP_AXI_SEL 0 macro
/Linux-v6.1/arch/arm/boot/dts/
Dmt7629.dtsi268 assigned-clocks = <&topckgen CLK_TOP_AXI_SEL>;
320 assigned-clocks = <&topckgen CLK_TOP_AXI_SEL>,
389 <&topckgen CLK_TOP_AXI_SEL>,
/Linux-v6.1/drivers/clk/mediatek/
Dclk-mt7629.c488 MUX_GATE(CLK_TOP_AXI_SEL, "axi_sel", axi_parents,
594 clk_prepare_enable(clk_data->hws[CLK_TOP_AXI_SEL]->clk); in mtk_topckgen_init()
Dclk-mt7622.c516 MUX_GATE(CLK_TOP_AXI_SEL, "axi_sel", axi_parents,
658 clk_prepare_enable(clk_data->hws[CLK_TOP_AXI_SEL]->clk); in mtk_topckgen_init()
Dclk-mt6795-topckgen.c452 TOP_MUX_GATE_NOSR(CLK_TOP_AXI_SEL, "axi_sel", axi_parents,
Dclk-mt8135.c353 MUX_GATE(CLK_TOP_AXI_SEL, "axi_sel", axi_parents,
Dclk-mt2701.c489 MUX_GATE_FLAGS(CLK_TOP_AXI_SEL, "axi_sel", axi_parents,
Dclk-mt2712.c739 MUX_GATE_FLAGS(CLK_TOP_AXI_SEL, "axi_sel", axi_parents, 0x040, 0, 3,
Dclk-mt6765.c368 MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_AXI_SEL, "axi_sel", axi_parents,
Dclk-mt8173.c543 MUX(CLK_TOP_AXI_SEL, "axi_sel", axi_parents, 0x0040, 0, 3),
Dclk-mt8192.c554 MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_AXI_SEL, "axi_sel",
Dclk-mt8365.c418 MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_AXI_SEL, "axi_sel", axi_parents,
/Linux-v6.1/arch/arm64/boot/dts/mediatek/
Dmt7622.dtsi259 <&topckgen CLK_TOP_AXI_SEL>;
718 <&topckgen CLK_TOP_AXI_SEL>;
Dmt2712e.dtsi780 <&topckgen CLK_TOP_AXI_SEL>,
791 <&topckgen CLK_TOP_AXI_SEL>,
Dmt8173.dtsi899 <&topckgen CLK_TOP_AXI_SEL>;
909 <&topckgen CLK_TOP_AXI_SEL>;