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Searched refs:reg_idx (Results 1 – 25 of 66) sorted by relevance

123

/Linux-v5.4/drivers/net/ethernet/intel/ixgbe/
Dixgbe_lib.c24 u16 reg_idx, pool; in ixgbe_cache_ring_dcb_sriov() local
36 reg_idx = vmdq->offset * __ALIGN_MASK(1, ~vmdq->mask); in ixgbe_cache_ring_dcb_sriov()
37 for (i = 0, pool = 0; i < adapter->num_rx_queues; i++, reg_idx++) { in ixgbe_cache_ring_dcb_sriov()
39 if ((reg_idx & ~vmdq->mask) >= tcs) { in ixgbe_cache_ring_dcb_sriov()
41 reg_idx = __ALIGN_MASK(reg_idx, ~vmdq->mask); in ixgbe_cache_ring_dcb_sriov()
43 adapter->rx_ring[i]->reg_idx = reg_idx; in ixgbe_cache_ring_dcb_sriov()
47 reg_idx = vmdq->offset * __ALIGN_MASK(1, ~vmdq->mask); in ixgbe_cache_ring_dcb_sriov()
48 for (i = 0; i < adapter->num_tx_queues; i++, reg_idx++) { in ixgbe_cache_ring_dcb_sriov()
50 if ((reg_idx & ~vmdq->mask) >= tcs) in ixgbe_cache_ring_dcb_sriov()
51 reg_idx = __ALIGN_MASK(reg_idx, ~vmdq->mask); in ixgbe_cache_ring_dcb_sriov()
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Dixgbe_main.c1228 IXGBE_READ_REG(hw, IXGBE_TDH(tx_ring->reg_idx)), in ixgbe_clean_tx_irq()
1229 IXGBE_READ_REG(hw, IXGBE_TDT(tx_ring->reg_idx)), in ixgbe_clean_tx_irq()
1287 reg_offset = IXGBE_DCA_TXCTRL(tx_ring->reg_idx); in ixgbe_update_tx_dca()
1291 reg_offset = IXGBE_DCA_TXCTRL_82599(tx_ring->reg_idx); in ixgbe_update_tx_dca()
1317 u8 reg_idx = rx_ring->reg_idx; in ixgbe_update_rx_dca() local
1340 IXGBE_WRITE_REG(hw, IXGBE_DCA_RXCTRL(reg_idx), rxctrl); in ixgbe_update_rx_dca()
2457 ixgbe_set_ivar(adapter, 0, ring->reg_idx, v_idx); in ixgbe_configure_msix()
2460 ixgbe_set_ivar(adapter, 1, ring->reg_idx, v_idx); in ixgbe_configure_msix()
3484 u8 reg_idx = ring->reg_idx; in ixgbe_configure_tx_ring() local
3491 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(reg_idx), 0); in ixgbe_configure_tx_ring()
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/Linux-v5.4/drivers/gpu/drm/msm/disp/dpu1/
Ddpu_hw_interrupts.c189 u32 reg_idx; member
777 int reg_idx; in dpu_hw_intr_dispatch_irq() local
793 for (reg_idx = 0; reg_idx < ARRAY_SIZE(dpu_intr_set); reg_idx++) { in dpu_hw_intr_dispatch_irq()
794 irq_status = intr->save_irq_status[reg_idx]; in dpu_hw_intr_dispatch_irq()
800 start_idx = reg_idx * 32; in dpu_hw_intr_dispatch_irq()
816 (dpu_irq_map[irq_idx].reg_idx == reg_idx)) { in dpu_hw_intr_dispatch_irq()
843 int reg_idx; in dpu_hw_intr_enable_irq() local
859 reg_idx = irq->reg_idx; in dpu_hw_intr_enable_irq()
860 reg = &dpu_intr_set[reg_idx]; in dpu_hw_intr_enable_irq()
863 cache_irq_mask = intr->cache_irq_mask[reg_idx]; in dpu_hw_intr_enable_irq()
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/Linux-v5.4/drivers/irqchip/
Dirq-mvebu-sei.c59 u32 reg_idx = SEI_IRQ_REG_IDX(d->hwirq); in mvebu_sei_ack_irq() local
62 sei->base + GICP_SECR(reg_idx)); in mvebu_sei_ack_irq()
68 u32 reg, reg_idx = SEI_IRQ_REG_IDX(d->hwirq); in mvebu_sei_mask_irq() local
73 reg = readl_relaxed(sei->base + GICP_SEMR(reg_idx)); in mvebu_sei_mask_irq()
75 writel_relaxed(reg, sei->base + GICP_SEMR(reg_idx)); in mvebu_sei_mask_irq()
82 u32 reg, reg_idx = SEI_IRQ_REG_IDX(d->hwirq); in mvebu_sei_unmask_irq() local
87 reg = readl_relaxed(sei->base + GICP_SEMR(reg_idx)); in mvebu_sei_unmask_irq()
89 writel_relaxed(reg, sei->base + GICP_SEMR(reg_idx)); in mvebu_sei_unmask_irq()
359 u32 reg_idx; in mvebu_sei_reset() local
362 for (reg_idx = 0; reg_idx < SEI_IRQ_REG_COUNT; reg_idx++) { in mvebu_sei_reset()
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/Linux-v5.4/drivers/misc/habanalabs/goya/
Dgoya_coresight.c236 if (params->reg_idx >= ARRAY_SIZE(debug_stm_regs)) { in goya_config_stm()
241 base_reg = debug_stm_regs[params->reg_idx] - CFG_BASE; in goya_config_stm()
306 if (params->reg_idx >= ARRAY_SIZE(debug_etf_regs)) { in goya_config_etf()
311 base_reg = debug_etf_regs[params->reg_idx] - CFG_BASE; in goya_config_etf()
468 if (params->reg_idx >= ARRAY_SIZE(debug_funnel_regs)) { in goya_config_funnel()
473 base_reg = debug_funnel_regs[params->reg_idx] - CFG_BASE; in goya_config_funnel()
489 if (params->reg_idx >= ARRAY_SIZE(debug_bmon_regs)) { in goya_config_bmon()
494 base_reg = debug_bmon_regs[params->reg_idx] - CFG_BASE; in goya_config_bmon()
518 if (params->reg_idx != GOYA_BMON_PCIE_MSTR_RD && in goya_config_bmon()
519 params->reg_idx != GOYA_BMON_PCIE_MSTR_WR && in goya_config_bmon()
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/Linux-v5.4/drivers/sh/intc/
Dhandle.c41 unsigned int *reg_idx, in _intc_mask_data() argument
48 while (mr && enum_id && *reg_idx < desc->hw.nr_mask_regs) { in _intc_mask_data()
49 mr = desc->hw.mask_regs + *reg_idx; in _intc_mask_data()
82 (*reg_idx)++; in _intc_mask_data()
109 unsigned int *reg_idx, in _intc_prio_data() argument
116 while (pr && enum_id && *reg_idx < desc->hw.nr_prio_regs) { in _intc_prio_data()
117 pr = desc->hw.prio_regs + *reg_idx; in _intc_prio_data()
151 (*reg_idx)++; in _intc_prio_data()
/Linux-v5.4/drivers/media/platform/mtk-vcodec/
Dmtk_vcodec_util.c25 unsigned int reg_idx) in mtk_vcodec_get_reg_addr() argument
29 if (!data || reg_idx >= NUM_MAX_VCODEC_REG_BASE) { in mtk_vcodec_get_reg_addr()
30 mtk_v4l2_err("Invalid arguments, reg_idx=%d", reg_idx); in mtk_vcodec_get_reg_addr()
33 return ctx->dev->reg_base[reg_idx]; in mtk_vcodec_get_reg_addr()
Dmtk_vcodec_util.h77 unsigned int reg_idx);
/Linux-v5.4/drivers/net/ethernet/intel/fm10k/
Dfm10k_pci.c875 u8 reg_idx = ring->reg_idx; in fm10k_configure_tx_ring() local
878 fm10k_write_reg(hw, FM10K_TXDCTL(reg_idx), 0); in fm10k_configure_tx_ring()
884 fm10k_write_reg(hw, FM10K_TDBAL(reg_idx), tdba & DMA_BIT_MASK(32)); in fm10k_configure_tx_ring()
885 fm10k_write_reg(hw, FM10K_TDBAH(reg_idx), tdba >> 32); in fm10k_configure_tx_ring()
886 fm10k_write_reg(hw, FM10K_TDLEN(reg_idx), size); in fm10k_configure_tx_ring()
889 fm10k_write_reg(hw, FM10K_TDH(reg_idx), 0); in fm10k_configure_tx_ring()
890 fm10k_write_reg(hw, FM10K_TDT(reg_idx), 0); in fm10k_configure_tx_ring()
893 ring->tail = &interface->uc_addr[FM10K_TDT(reg_idx)]; in fm10k_configure_tx_ring()
905 fm10k_write_reg(hw, FM10K_TXINT(reg_idx), txint); in fm10k_configure_tx_ring()
908 fm10k_write_reg(hw, FM10K_PFVTCTL(reg_idx), in fm10k_configure_tx_ring()
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Dfm10k_main.c1133 head = fm10k_read_reg(hw, FM10K_TDH(ring->reg_idx)); in fm10k_get_tx_pending()
1134 tail = fm10k_read_reg(hw, FM10K_TDT(ring->reg_idx)); in fm10k_get_tx_pending()
1298 fm10k_read_reg(hw, FM10K_TDH(tx_ring->reg_idx)), in fm10k_clean_tx_irq()
1299 fm10k_read_reg(hw, FM10K_TDT(tx_ring->reg_idx)), in fm10k_clean_tx_irq()
1888 interface->tx_ring[offset + i]->reg_idx = q_idx; in fm10k_cache_ring_qos()
1890 interface->rx_ring[offset + i]->reg_idx = q_idx; in fm10k_cache_ring_qos()
1910 interface->rx_ring[i]->reg_idx = i; in fm10k_cache_ring_rss()
1913 interface->tx_ring[i]->reg_idx = i; in fm10k_cache_ring_rss()
/Linux-v5.4/drivers/net/ethernet/intel/ixgbevf/
Dixgbevf_main.c203 u32 head = IXGBE_READ_REG(hw, IXGBE_VFTDH(ring->reg_idx)); in ixgbevf_get_tx_pending()
204 u32 tail = IXGBE_READ_REG(hw, IXGBE_VFTDT(ring->reg_idx)); in ixgbevf_get_tx_pending()
387 IXGBE_READ_REG(hw, IXGBE_VFTDH(tx_ring->reg_idx)), in ixgbevf_clean_tx_irq()
388 IXGBE_READ_REG(hw, IXGBE_VFTDT(tx_ring->reg_idx)), in ixgbevf_clean_tx_irq()
1357 ixgbevf_set_ivar(adapter, 0, ring->reg_idx, v_idx); in ixgbevf_configure_msix()
1360 ixgbevf_set_ivar(adapter, 1, ring->reg_idx, v_idx); in ixgbevf_configure_msix()
1683 u8 reg_idx = ring->reg_idx; in ixgbevf_configure_tx_ring() local
1686 IXGBE_WRITE_REG(hw, IXGBE_VFTXDCTL(reg_idx), IXGBE_TXDCTL_SWFLSH); in ixgbevf_configure_tx_ring()
1689 IXGBE_WRITE_REG(hw, IXGBE_VFTDBAL(reg_idx), tdba & DMA_BIT_MASK(32)); in ixgbevf_configure_tx_ring()
1690 IXGBE_WRITE_REG(hw, IXGBE_VFTDBAH(reg_idx), tdba >> 32); in ixgbevf_configure_tx_ring()
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/Linux-v5.4/drivers/bus/
Dimx-weim.c136 int reg_idx, num_regs; in weim_timing_setup() local
158 for (reg_idx = 0; reg_idx < num_regs; reg_idx++) { in weim_timing_setup()
161 reg_idx * OF_REG_SIZE, &cs_idx); in weim_timing_setup()
/Linux-v5.4/sound/soc/codecs/
Dmt6351.c328 int idx, old_idx, offset, reg_idx; in hp_gain_ramp_set() local
345 reg_idx = old_idx; in hp_gain_ramp_set()
348 reg_idx = idx > old_idx ? reg_idx + 1 : reg_idx - 1; in hp_gain_ramp_set()
351 if ((reg_idx >= 0 && reg_idx <= 0x12) || reg_idx == 0x1f) { in hp_gain_ramp_set()
355 (reg_idx << 7) | reg_idx); in hp_gain_ramp_set()
Dmt6358.c376 static bool is_valid_hp_pga_idx(int reg_idx) in is_valid_hp_pga_idx() argument
378 return (reg_idx >= DL_GAIN_8DB && reg_idx <= DL_GAIN_N_10DB) || in is_valid_hp_pga_idx()
379 reg_idx == DL_GAIN_N_40DB; in is_valid_hp_pga_idx()
384 int offset = 0, count = 0, reg_idx; in headset_volume_ramp() local
400 reg_idx = from + count; in headset_volume_ramp()
402 reg_idx = from - count; in headset_volume_ramp()
404 if (is_valid_hp_pga_idx(reg_idx)) { in headset_volume_ramp()
408 (reg_idx << 7) | reg_idx); in headset_volume_ramp()
/Linux-v5.4/drivers/net/ethernet/intel/i40e/
Di40e_virtchnl_pf.c292 u32 reg, reg_idx; in i40e_config_irq_link_list() local
298 reg_idx = I40E_VPINT_LNKLST0(vf->vf_id); in i40e_config_irq_link_list()
300 reg_idx = I40E_VPINT_LNKLSTN( in i40e_config_irq_link_list()
306 wr32(hw, reg_idx, I40E_VPINT_LNKLST0_FIRSTQ_INDX_MASK); in i40e_config_irq_link_list()
331 wr32(hw, reg_idx, reg); in i40e_config_irq_link_list()
336 reg_idx = I40E_QINT_RQCTL(pf_queue_id); in i40e_config_irq_link_list()
340 reg_idx = I40E_QINT_TQCTL(pf_queue_id); in i40e_config_irq_link_list()
365 wr32(hw, reg_idx, reg); in i40e_config_irq_link_list()
404 u32 v_idx, reg_idx, reg; in i40e_release_iwarp_qvlist() local
414 reg_idx = (msix_vf - 1) * vf->vf_id + qv_info->ceq_idx; in i40e_release_iwarp_qvlist()
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Di40e_client.c150 u32 reg_idx; in i40e_client_release_qvlist() local
155 reg_idx = I40E_PFINT_LNKLSTN(qv_info->v_idx - 1); in i40e_client_release_qvlist()
156 wr32(&pf->hw, reg_idx, I40E_PFINT_LNKLSTN_FIRSTQ_INDX_MASK); in i40e_client_release_qvlist()
580 u32 v_idx, i, reg_idx, reg; in i40e_client_setup_qvlist() local
600 reg_idx = I40E_PFINT_LNKLSTN(v_idx - 1); in i40e_client_setup_qvlist()
604 wr32(hw, reg_idx, I40E_PFINT_LNKLSTN_FIRSTQ_INDX_MASK); in i40e_client_setup_qvlist()
610 wr32(hw, reg_idx, reg); in i40e_client_setup_qvlist()
/Linux-v5.4/drivers/net/ethernet/intel/ice/
Dice_lib.c1309 ring->reg_idx = vsi->txq_map[i]; in ice_vsi_alloc_rings()
1327 ring->reg_idx = vsi->rxq_map[i]; in ice_vsi_alloc_rings()
1733 pf_q = ring->reg_idx; in ice_vsi_cfg_txq()
1896 wr32(hw, GLINT_ITR(rc->itr_idx, q_vector->reg_idx), in ice_cfg_itr()
1910 wr32(hw, GLINT_ITR(rc->itr_idx, q_vector->reg_idx), in ice_cfg_itr()
1993 u16 reg_idx = q_vector->reg_idx; in ice_vsi_cfg_msix() local
1997 wr32(hw, GLINT_RATE(reg_idx), in ice_vsi_cfg_msix()
2012 ice_cfg_txq_interrupt(vsi, txq, reg_idx, in ice_vsi_cfg_msix()
2018 ice_cfg_rxq_interrupt(vsi, rxq, reg_idx, in ice_vsi_cfg_msix()
2143 wr32(hw, GLINT_DYN_CTL(q_vector->reg_idx), in ice_trigger_sw_intr()
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/Linux-v5.4/arch/x86/events/intel/
Duncore_nhmex.c772 int reg_idx = 0; in nhmex_mbox_hw_config() local
790 reg_idx = 1; in nhmex_mbox_hw_config()
791 else if (WARN_ON_ONCE(reg_idx > 0)) in nhmex_mbox_hw_config()
794 reg1->idx &= ~(0xff << (reg_idx * 8)); in nhmex_mbox_hw_config()
795 reg1->reg &= ~(0xffff << (reg_idx * 16)); in nhmex_mbox_hw_config()
796 reg1->idx |= nhmex_mbox_extra_reg_idx(er) << (reg_idx * 8); in nhmex_mbox_hw_config()
797 reg1->reg |= msr << (reg_idx * 16); in nhmex_mbox_hw_config()
799 reg_idx++; in nhmex_mbox_hw_config()
805 if (reg_idx == 2) { in nhmex_mbox_hw_config()
/Linux-v5.4/drivers/hwmon/
Dw83791d.c771 u8 reg_idx = 0; in store_pwmenable() local
784 reg_idx = 0; in store_pwmenable()
789 reg_idx = 0; in store_pwmenable()
794 reg_idx = 1; in store_pwmenable()
800 reg_cfg_tmp = w83791d_read(client, W83791D_REG_FAN_CFG[reg_idx]); in store_pwmenable()
804 w83791d_write(client, W83791D_REG_FAN_CFG[reg_idx], reg_cfg_tmp); in store_pwmenable()
878 u8 reg_idx = 0; in store_temp_tolerance() local
887 reg_idx = 0; in store_temp_tolerance()
892 reg_idx = 0; in store_temp_tolerance()
897 reg_idx = 1; in store_temp_tolerance()
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/Linux-v5.4/drivers/net/ethernet/intel/igc/
Digc_main.c525 int reg_idx = ring->reg_idx; in igc_configure_rx_ring() local
530 wr32(IGC_RXDCTL(reg_idx), 0); in igc_configure_rx_ring()
533 wr32(IGC_RDBAL(reg_idx), in igc_configure_rx_ring()
535 wr32(IGC_RDBAH(reg_idx), rdba >> 32); in igc_configure_rx_ring()
536 wr32(IGC_RDLEN(reg_idx), in igc_configure_rx_ring()
540 ring->tail = adapter->io_addr + IGC_RDT(reg_idx); in igc_configure_rx_ring()
541 wr32(IGC_RDH(reg_idx), 0); in igc_configure_rx_ring()
556 wr32(IGC_SRRCTL(reg_idx), srrctl); in igc_configure_rx_ring()
573 wr32(IGC_RXDCTL(reg_idx), rxdctl); in igc_configure_rx_ring()
604 int reg_idx = ring->reg_idx; in igc_configure_tx_ring() local
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/Linux-v5.4/drivers/perf/hisilicon/
Dhisi_uncore_hha_pmu.c81 u32 reg, reg_idx, shift, val; in hisi_hha_pmu_write_evtype() local
91 reg_idx = idx % 4; in hisi_hha_pmu_write_evtype()
92 shift = 8 * reg_idx; in hisi_hha_pmu_write_evtype()
Dhisi_uncore_l3c_pmu.c80 u32 reg, reg_idx, shift, val; in hisi_l3c_pmu_write_evtype() local
90 reg_idx = idx % 4; in hisi_l3c_pmu_write_evtype()
91 shift = 8 * reg_idx; in hisi_l3c_pmu_write_evtype()
/Linux-v5.4/drivers/perf/
Dqcom_l2_pmu.c85 #define reg_idx(reg, i) (((i) * IA_L2_REG_OFFSET) + reg##_BASE) macro
235 set_l2_indirect_reg(reg_idx(IA_L2PMXEVCNTR, idx), value); in cluster_pmu_counter_set_value()
245 value = get_l2_indirect_reg(reg_idx(IA_L2PMXEVCNTR, idx)); in cluster_pmu_counter_get_value()
277 set_l2_indirect_reg(reg_idx(IA_L2PMXEVCNTCR, ctr), val); in cluster_pmu_set_evcntcr()
282 set_l2_indirect_reg(reg_idx(IA_L2PMXEVTYPER, ctr), val); in cluster_pmu_set_evtyper()
318 set_l2_indirect_reg(reg_idx(IA_L2PMXEVFILTER, ctr), val); in cluster_pmu_set_evfilter_sys_mode()
/Linux-v5.4/drivers/pci/controller/
Dpcie-iproc.c1423 unsigned int reg_idx; in iproc_pcie_rev_init() local
1479 for (reg_idx = 1; reg_idx < IPROC_PCIE_MAX_NUM_REG; reg_idx++) in iproc_pcie_rev_init()
1480 pcie->reg_offsets[reg_idx] = regs[reg_idx] ? in iproc_pcie_rev_init()
1481 regs[reg_idx] : IPROC_PCIE_REG_INVALID; in iproc_pcie_rev_init()
/Linux-v5.4/drivers/media/platform/coda/
Dcoda-bit.c74 CODA_REG_BIT_FRM_DIS_FLG(ctx->reg_idx)); in coda_command_async()
154 rd_ptr = coda_read(dev, CODA_REG_BIT_RD_PTR(ctx->reg_idx)); in coda_kfifo_sync_from_device()
168 coda_write(dev, rd_ptr, CODA_REG_BIT_RD_PTR(ctx->reg_idx)); in coda_kfifo_sync_to_device_full()
170 coda_write(dev, wr_ptr, CODA_REG_BIT_WR_PTR(ctx->reg_idx)); in coda_kfifo_sync_to_device_full()
180 coda_write(dev, wr_ptr, CODA_REG_BIT_WR_PTR(ctx->reg_idx)); in coda_kfifo_sync_to_device_write()
670 *size = coda_read(dev, CODA_REG_BIT_WR_PTR(ctx->reg_idx)) - in coda_encode_header()
1095 coda_write(dev, bitstream_buf, CODA_REG_BIT_RD_PTR(ctx->reg_idx)); in coda_start_encoding()
1096 coda_write(dev, bitstream_buf, CODA_REG_BIT_WR_PTR(ctx->reg_idx)); in coda_start_encoding()
1645 wr_ptr = coda_read(dev, CODA_REG_BIT_WR_PTR(ctx->reg_idx)); in coda_finish_encode()
1869 coda_write(dev, 0, CODA_REG_BIT_FRM_DIS_FLG(ctx->reg_idx)); in __coda_decoder_seq_init()
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