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Searched refs:mt76_clear (Results 1 – 25 of 27) sorted by relevance

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/Linux-v5.4/drivers/net/wireless/mediatek/mt76/mt76x2/
Dpci_init.c23 mt76_clear(dev, MT_PBF_SYS_CTRL, val); in mt76x2_mac_pbf_init()
93 mt76_clear(dev, MT_MAC_SYS_CTRL, in mt76x2_mac_reset()
98 mt76_clear(dev, MT_COEXCFG0, MT_COEXCFG0_COEX_EN); in mt76x2_mac_reset()
101 mt76_clear(dev, MT_TX_ALC_CFG_4, BIT(31)); in mt76x2_mac_reset()
109 mt76_clear(dev, MT_FCE_L2_STUFF, MT_FCE_L2_STUFF_WR_MPDU_LEN_EN); in mt76x2_mac_reset()
171 mt76_clear(dev, 0x1001c, 0xff); in mt76x2_power_on_rf_patch()
180 mt76_clear(dev, 0x10130, BIT(16)); in mt76x2_power_on_rf_patch()
200 mt76_clear(dev, 0x10130, BIT(2) << shift); in mt76x2_power_on_rf()
222 mt76_clear(dev, MT_WLAN_MTC_CTRL, 0x7f << 16); in mt76x2_power_on()
225 mt76_clear(dev, MT_WLAN_MTC_CTRL, 0xf << 24); in mt76x2_power_on()
[all …]
Dusb_mac.c57 mt76_clear(dev, MT_FCE_L2_STUFF, MT_FCE_L2_STUFF_WR_MPDU_LEN_EN); in mt76x2u_mac_fixup_xtal()
90 mt76_clear(dev, MT_MAC_SYS_CTRL, in mt76x2u_mac_reset()
95 mt76_clear(dev, MT_COEXCFG0, MT_COEXCFG0_COEX_EN); in mt76x2u_mac_reset()
98 mt76_clear(dev, MT_TX_ALC_CFG_4, BIT(31)); in mt76x2u_mac_reset()
134 mt76_clear(dev, MT_TXOP_CTRL_CFG, MT_TXOP_ED_CCA_EN); in mt76x2u_mac_stop()
135 mt76_clear(dev, MT_TXOP_HLDR_ET, MT_TXOP_HLDR_TX40M_BLK_EN); in mt76x2u_mac_stop()
155 mt76_clear(dev, MT_MAC_SYS_CTRL, in mt76x2u_mac_stop()
171 mt76_clear(dev, MT_BBP(CORE, 4), BIT(1)); in mt76x2u_mac_stop()
174 mt76_clear(dev, MT_BBP(CORE, 4), BIT(0)); in mt76x2u_mac_stop()
Dmac.c15 mt76_clear(dev, MT_TXOP_CTRL_CFG, MT_TXOP_ED_CCA_EN); in mt76x2_mac_stop()
16 mt76_clear(dev, MT_TXOP_HLDR_ET, MT_TXOP_HLDR_TX40M_BLK_EN); in mt76x2_mac_stop()
38 mt76_clear(dev, MT_BBP(CORE, 4), BIT(1)); in mt76x2_mac_stop()
41 mt76_clear(dev, MT_BBP(CORE, 4), BIT(0)); in mt76x2_mac_stop()
Dusb_init.c33 mt76_clear(dev, MT_VEND_ADDR(CFG, 0x1c), 0xff); in mt76x2u_power_on_rf_patch()
42 mt76_clear(dev, MT_VEND_ADDR(CFG, 0x130), BIT(16)); in mt76x2u_power_on_rf_patch()
62 mt76_clear(dev, MT_VEND_ADDR(CFG, 0x130), BIT(2) << shift); in mt76x2u_power_on_rf()
84 mt76_clear(dev, MT_VEND_ADDR(CFG, 0x148), 0x7f << 16); in mt76x2u_power_on()
87 mt76_clear(dev, MT_VEND_ADDR(CFG, 0x148), 0xf << 24); in mt76x2u_power_on()
91 mt76_clear(dev, MT_VEND_ADDR(CFG, 0x148), 0xfff); in mt76x2u_power_on()
94 mt76_clear(dev, MT_VEND_ADDR(CFG, 0x1204), BIT(3)); in mt76x2u_power_on()
100 mt76_clear(dev, MT_VEND_ADDR(CFG, 0x64), BIT(18)); in mt76x2u_power_on()
Dpci_phy.c80 mt76_clear(dev, MT_BBP(IBI, 9), BIT(11)); in mt76x2_phy_set_antenna()
81 mt76_clear(dev, MT_BBP(TXBE, 5), 3); in mt76x2_phy_set_antenna()
91 mt76_clear(dev, MT_BBP(IBI, 9), BIT(11)); in mt76x2_phy_set_antenna()
107 mt76_clear(dev, MT_BBP(CORE, 32), GENMASK(21, 20)); in mt76x2_phy_set_antenna()
108 mt76_clear(dev, MT_BBP(CORE, 33), GENMASK(12, 9)); in mt76x2_phy_set_antenna()
/Linux-v5.4/drivers/net/wireless/mediatek/mt76/mt76x0/
Dinit.c95 mt76_clear(dev, MT_MAC_SYS_CTRL, in mt76x0_reset_csr_bbp()
135 mt76_clear(dev, MT_MAC_SYS_CTRL, 0x3); in mt76x0_init_mac_registers()
140 mt76_clear(dev, MT_FCE_L2_STUFF, MT_FCE_L2_STUFF_WR_MPDU_LEN_EN); in mt76x0_init_mac_registers()
182 mt76_clear(dev, MT_TXOP_CTRL_CFG, MT_TXOP_ED_CCA_EN); in mt76x0_mac_stop()
193 mt76_clear(dev, MT_MAC_SYS_CTRL, MT_MAC_SYS_CTRL_ENABLE_RX | in mt76x0_mac_stop()
Dpci.c36 mt76_clear(dev, MT_WPDMA_GLO_CFG, MT_WPDMA_GLO_CFG_TX_DMA_EN); in mt76x0e_stop_hw()
43 mt76_clear(dev, MT_WPDMA_GLO_CFG, MT_WPDMA_GLO_CFG_RX_DMA_EN); in mt76x0e_stop_hw()
125 mt76_clear(dev, MT_COEXCFG0, BIT(0)); in mt76x0e_register_device()
132 mt76_clear(dev, 0x110, BIT(9)); in mt76x0e_register_device()
Dphy.c359 mt76_clear(dev, MT_RF_MISC, 0xc); in mt76x0_phy_set_chan_rf_params()
468 mt76_clear(dev, MT_COEXCFG0, BIT(2)); in mt76x0_phy_ant_select()
518 mt76_clear(dev, MT_BBP(CORE, 4), BIT(0)); in mt76x0_phy_tssi_dc_calibrate()
536 mt76_clear(dev, MT_BBP(CORE, 4), BIT(0)); in mt76x0_phy_tssi_dc_calibrate()
553 mt76_clear(dev, MT_BBP(CORE, 34), BIT(4)); in mt76x0_phy_tssi_adc_calibrate()
999 mt76_clear(dev, MT_BBP(CORE, 1), 0x20); in mt76x0_phy_set_channel()
1032 mt76_clear(dev, MT_BBP(CORE, 34), BIT(4)); in mt76x0_phy_temp_sensor()
/Linux-v5.4/drivers/net/wireless/mediatek/mt76/
Dmt76x02_phy.c44 mt76_clear(dev, MT_BBP(TXBE, 5), 0x3); in mt76x02_phy_set_txdac()
156 mt76_clear(dev, MT_TX_BAND_CFG, MT_TX_BAND_CFG_5G); in mt76x02_phy_set_band()
159 mt76_clear(dev, MT_TX_BAND_CFG, MT_TX_BAND_CFG_2G); in mt76x02_phy_set_band()
Dmt76x02_mac.c227 mt76_clear(dev, MT_AUTO_RSP_CFG, MT_AUTO_RSP_PREAMB_SHORT); in mt76x02_mac_set_short_preamble()
996 mt76_clear(dev, MT_MAC_SYS_CTRL, MT_MAC_SYS_CTRL_ENABLE_TX); in mt76x02_edcca_tx_enable()
997 mt76_clear(dev, MT_AUTO_RSP_CFG, MT_AUTO_RSP_EN); in mt76x02_edcca_tx_enable()
999 mt76_clear(dev, MT_TX_PIN_CFG, MT_TX_PIN_CFG_TXANT); in mt76x02_edcca_tx_enable()
1000 mt76_clear(dev, MT_TX_PIN_CFG, MT_TX_PIN_CFG_RXANT); in mt76x02_edcca_tx_enable()
1014 mt76_clear(dev, MT_TX_LINK_CFG, MT_TX_CFACK_EN); in mt76x02_edcca_init()
1021 mt76_clear(dev, MT_TXOP_CTRL_CFG, MT_TXOP_ED_CCA_EN); in mt76x02_edcca_init()
1028 mt76_clear(dev, MT_TXOP_HLDR_ET, in mt76x02_edcca_init()
Dmt76x02_mmio.c321 mt76_clear(dev, MT_WPDMA_GLO_CFG, in mt76x02_dma_enable()
458 mt76_clear(dev, MT_BEACON_TIME_CFG, in mt76x02_watchdog_reset()
465 mt76_clear(dev, MT_TXOP_CTRL_CFG, MT_TXOP_ED_CCA_EN); in mt76x02_watchdog_reset()
467 mt76_clear(dev, MT_WPDMA_GLO_CFG, in mt76x02_watchdog_reset()
Dmt76x02_beacon.c134 mt76_clear(dev, MT_BEACON_TIME_CFG, in mt76x02_mac_set_beacon_enable()
249 mt76_clear(dev, MT_BEACON_TIME_CFG, (MT_BEACON_TIME_CFG_TIMER_EN | in mt76x02_init_beacon_config()
Dmt76x02_usb_core.c255 mt76_clear(dev, MT_BEACON_TIME_CFG, in mt76x02u_exit_beacon_config()
/Linux-v5.4/drivers/net/wireless/mediatek/mt76/mt7603/
Dbeacon.c157 mt76_clear(dev, MT_ARB_SCR, MT_ARB_SCR_BCNQ_OPMODE_MASK); in mt7603_beacon_set_timer()
170 mt76_clear(dev, MT_ARB_SCR, MT_ARB_SCR_TBTT_BCN_PRIO); in mt7603_beacon_set_timer()
187 mt76_clear(dev, MT_LPON_SBTOR(0), MT_LPON_SBTOR_SUB_BSS_EN); in mt7603_beacon_set_timer()
Dmac.c70 mt76_clear(dev, MT_ARB_SCR, in mt7603_mac_set_timing()
239 mt76_clear(dev, MT_WTBL1_OR, MT_WTBL1_OR_PSM_WRITE); in mt7603_wtbl_set_ps()
286 mt76_clear(dev, MT_WTBL1_OR, MT_WTBL1_OR_PSM_WRITE); in mt7603_wtbl_clear()
358 mt76_clear(dev, addr + (15 * 4), tid_mask); in mt7603_mac_tx_ba_reset()
1181 mt76_clear(dev, MT_MCU_DEBUG_RESET, MT_MCU_DEBUG_RESET_PSE_S); in mt7603_pse_reset()
1190 mt76_clear(dev, MT_MCU_DEBUG_RESET, MT_MCU_DEBUG_RESET_PSE); in mt7603_pse_reset()
1193 mt76_clear(dev, MT_MCU_DEBUG_RESET, MT_MCU_DEBUG_RESET_QUEUES); in mt7603_pse_reset()
1218 mt76_clear(dev, MT_ARB_SCR, in mt7603_mac_start()
1229 mt76_clear(dev, MT_WF_ARB_RQCR, MT_WF_ARB_RQCR_RX_START); in mt7603_mac_stop()
1240 mt76_clear(dev, addr, in mt7603_pse_client_reset()
[all …]
Ddma.c173 mt76_clear(dev, MT_WPDMA_GLO_CFG, in mt7603_dma_init()
234 mt76_clear(dev, MT_WPDMA_GLO_CFG, in mt7603_dma_cleanup()
Dinit.c176 mt76_clear(dev, MT_WF_RMAC_TMR_PA, BIT(31)); in mt7603_mac_init()
258 mt76_clear(dev, MT_SEC_SCR, MT_SEC_SCR_MASK_ORDER); in mt7603_mac_init()
259 mt76_clear(dev, MT_SEC_SCR, BIT(18)); in mt7603_mac_init()
Dmcu.c249 mt76_clear(dev, MT_SCH_4, MT_SCH_4_FORCE_QID | MT_SCH_4_BYPASS); in mt7603_load_firmware()
252 mt76_clear(dev, MT_SCH_4, BIT(8)); in mt7603_load_firmware()
Dmain.c117 mt76_clear(dev, MT_MIB_CTL, MT_MIB_CTL_ED_TIME); in mt7603_init_edcca()
179 mt76_clear(dev, MT_MIB_CTL, MT_MIB_CTL_READ_CLR_DIS); in mt7603_set_channel()
/Linux-v5.4/drivers/net/wireless/mediatek/mt76/mt7615/
Ddma.c148 mt76_clear(dev, 0x7000, BIT(23)); in mt7615_dma_init()
207 mt76_clear(dev, MT_WPDMA_GLO_CFG, in mt7615_dma_cleanup()
Dmac.c723 mt76_clear(dev, addr + 2 * 4, MT_WTBL_W2_KEY_TYPE); in mt7615_mac_wtbl_update_cipher()
1107 mt76_clear(dev, MT_WF_PHY_B0_MIN_PRI_PWR, in mt7615_mac_set_scs()
1109 mt76_clear(dev, MT_WF_PHY_B1_MIN_PRI_PWR, in mt7615_mac_set_scs()
1122 mt76_clear(dev, MT_WF_PHY_R0_B0_PHYMUX_5, GENMASK(22, 20)); in mt7615_mac_cca_stats_reset()
/Linux-v5.4/drivers/net/wireless/mediatek/mt7601u/
Dinit.c264 mt76_clear(dev, MT_BEACON_TIME_CFG, MT_BEACON_TIME_CFG_TIMER_EN | in mt7601u_mac_stop_hw()
281 mt76_clear(dev, MT_MAC_SYS_CTRL, MT_MAC_SYS_CTRL_ENABLE_RX | in mt7601u_mac_stop_hw()
383 mt76_clear(dev, MT_BEACON_TIME_CFG, (MT_BEACON_TIME_CFG_TIMER_EN | in mt7601u_init_hardware()
Dmain.c229 mt76_clear(dev, MT_WCID_DROP(idx), MT_WCID_DROP_MASK(idx)); in mt7601u_sta_add()
364 mt76_clear(dev, MT_WCID_ADDR(msta->wcid.idx) + 4, in mt76_ampdu_action()
Dmac.c264 mt76_clear(dev, MT_AUTO_RSP_CFG, MT_AUTO_RSP_PREAMB_SHORT); in mt7601u_mac_set_short_preamble()
298 mt76_clear(dev, MT_MAC_SYS_CTRL, MT_MAC_SYS_CTRL_RESET_CSR); in mt7601u_check_mac_err()
Dmt7601u.h321 static inline u32 mt76_clear(struct mt7601u_dev *dev, u32 offset, u32 val) in mt76_clear() function

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