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Searched refs:dpm_table (Results 1 – 19 of 19) sorted by relevance

/Linux-v5.4/drivers/gpu/drm/amd/powerplay/hwmgr/
Dvega12_hwmgr.c519 struct vega12_single_dpm_table *dpm_table, PPCLK_e clk_id) in vega12_setup_single_dpm_table() argument
529 dpm_table->count = num_of_levels; in vega12_setup_single_dpm_table()
536 dpm_table->dpm_levels[i].value = clk; in vega12_setup_single_dpm_table()
537 dpm_table->dpm_levels[i].enabled = true; in vega12_setup_single_dpm_table()
556 struct vega12_single_dpm_table *dpm_table; in vega12_setup_default_dpm_tables() local
559 memset(&data->dpm_table, 0, sizeof(data->dpm_table)); in vega12_setup_default_dpm_tables()
562 dpm_table = &(data->dpm_table.soc_table); in vega12_setup_default_dpm_tables()
564 ret = vega12_setup_single_dpm_table(hwmgr, dpm_table, PPCLK_SOCCLK); in vega12_setup_default_dpm_tables()
569 dpm_table->count = 1; in vega12_setup_default_dpm_tables()
570 dpm_table->dpm_levels[0].value = data->vbios_boot_state.soc_clock / 100; in vega12_setup_default_dpm_tables()
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Dvega20_hwmgr.c560 struct vega20_single_dpm_table *dpm_table, PPCLK_e clk_id) in vega20_setup_single_dpm_table() argument
570 dpm_table->count = num_of_levels; in vega20_setup_single_dpm_table()
577 dpm_table->dpm_levels[i].value = clk; in vega20_setup_single_dpm_table()
578 dpm_table->dpm_levels[i].enabled = true; in vega20_setup_single_dpm_table()
588 struct vega20_single_dpm_table *dpm_table; in vega20_setup_gfxclk_dpm_table() local
591 dpm_table = &(data->dpm_table.gfx_table); in vega20_setup_gfxclk_dpm_table()
593 ret = vega20_setup_single_dpm_table(hwmgr, dpm_table, PPCLK_GFXCLK); in vega20_setup_gfxclk_dpm_table()
598 dpm_table->count = 1; in vega20_setup_gfxclk_dpm_table()
599 dpm_table->dpm_levels[0].value = data->vbios_boot_state.gfx_clock / 100; in vega20_setup_gfxclk_dpm_table()
609 struct vega20_single_dpm_table *dpm_table; in vega20_setup_memclk_dpm_table() local
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Dvega10_hwmgr.c1224 struct vega10_single_dpm_table *dpm_table, in vega10_setup_default_single_dpm_table() argument
1229 dpm_table->count = 0; in vega10_setup_default_single_dpm_table()
1232 if (i == 0 || dpm_table->dpm_levels[dpm_table->count - 1].value <= in vega10_setup_default_single_dpm_table()
1234 dpm_table->dpm_levels[dpm_table->count].value = in vega10_setup_default_single_dpm_table()
1236 dpm_table->dpm_levels[dpm_table->count].enabled = true; in vega10_setup_default_single_dpm_table()
1237 dpm_table->count++; in vega10_setup_default_single_dpm_table()
1244 struct vega10_pcie_table *pcie_table = &(data->dpm_table.pcie_table); in vega10_setup_default_pcie_table()
1295 struct vega10_single_dpm_table *dpm_table; in vega10_setup_default_dpm_tables() local
1337 dpm_table = &(data->dpm_table.soc_table); in vega10_setup_default_dpm_tables()
1339 dpm_table, in vega10_setup_default_dpm_tables()
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Dsmu7_hwmgr.c554 phm_reset_single_dpm_table(&data->dpm_table.pcie_speed_table, in smu7_setup_default_pcie_table()
565 phm_setup_pcie_table_entry(&data->dpm_table.pcie_speed_table, i - 1, in smu7_setup_default_pcie_table()
571 data->dpm_table.pcie_speed_table.count = max_entry - 1; in smu7_setup_default_pcie_table()
575 phm_setup_pcie_table_entry(&data->dpm_table.pcie_speed_table, 0, in smu7_setup_default_pcie_table()
580 phm_setup_pcie_table_entry(&data->dpm_table.pcie_speed_table, 1, in smu7_setup_default_pcie_table()
585 phm_setup_pcie_table_entry(&data->dpm_table.pcie_speed_table, 2, in smu7_setup_default_pcie_table()
590 phm_setup_pcie_table_entry(&data->dpm_table.pcie_speed_table, 3, in smu7_setup_default_pcie_table()
595 phm_setup_pcie_table_entry(&data->dpm_table.pcie_speed_table, 4, in smu7_setup_default_pcie_table()
600 phm_setup_pcie_table_entry(&data->dpm_table.pcie_speed_table, 5, in smu7_setup_default_pcie_table()
606 data->dpm_table.pcie_speed_table.count = 6; in smu7_setup_default_pcie_table()
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Dsmu_helper.c350 struct vi_dpm_table *dpm_table = (struct vi_dpm_table *)table; in phm_reset_single_dpm_table() local
352 dpm_table->count = count > max ? max : count; in phm_reset_single_dpm_table()
354 for (i = 0; i < dpm_table->count; i++) in phm_reset_single_dpm_table()
355 dpm_table->dpm_level[i].enabled = false; in phm_reset_single_dpm_table()
365 struct vi_dpm_table *dpm_table = (struct vi_dpm_table *)table; in phm_setup_pcie_table_entry() local
366 dpm_table->dpm_level[index].value = pcie_gen; in phm_setup_pcie_table_entry()
367 dpm_table->dpm_level[index].param1 = pcie_lanes; in phm_setup_pcie_table_entry()
368 dpm_table->dpm_level[index].enabled = 1; in phm_setup_pcie_table_entry()
375 struct vi_dpm_table *dpm_table = (struct vi_dpm_table *)table; in phm_get_dpm_level_enable_mask_value() local
377 for (i = dpm_table->count; i > 0; i--) { in phm_get_dpm_level_enable_mask_value()
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Dsmu7_hwmgr.h204 struct smu7_dpm_table dpm_table; member
Dvega10_hwmgr.h311 struct vega10_dpm_table dpm_table; member
Dvega12_hwmgr.h314 struct vega12_dpm_table dpm_table; member
Dvega20_hwmgr.h437 struct vega20_dpm_table dpm_table; member
/Linux-v5.4/drivers/gpu/drm/amd/powerplay/
Dvega20_ppt.c716 struct vega20_dpm_table *dpm_table = NULL; in vega20_set_default_dpm_table() local
719 dpm_table = smu_dpm->dpm_context; in vega20_set_default_dpm_table()
722 single_dpm_table = &(dpm_table->soc_table); in vega20_set_default_dpm_table()
738 single_dpm_table = &(dpm_table->gfx_table); in vega20_set_default_dpm_table()
754 single_dpm_table = &(dpm_table->mem_table); in vega20_set_default_dpm_table()
770 single_dpm_table = &(dpm_table->eclk_table); in vega20_set_default_dpm_table()
785 single_dpm_table = &(dpm_table->vclk_table); in vega20_set_default_dpm_table()
800 single_dpm_table = &(dpm_table->dclk_table); in vega20_set_default_dpm_table()
815 single_dpm_table = &(dpm_table->dcef_table); in vega20_set_default_dpm_table()
831 single_dpm_table = &(dpm_table->pixel_table); in vega20_set_default_dpm_table()
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Darcturus_ppt.c408 struct arcturus_dpm_table *dpm_table = NULL; in arcturus_set_default_dpm_table() local
411 dpm_table = smu_dpm->dpm_context; in arcturus_set_default_dpm_table()
414 single_dpm_table = &(dpm_table->soc_table); in arcturus_set_default_dpm_table()
429 single_dpm_table = &(dpm_table->gfx_table); in arcturus_set_default_dpm_table()
444 single_dpm_table = &(dpm_table->mem_table); in arcturus_set_default_dpm_table()
459 single_dpm_table = &(dpm_table->fclk_table); in arcturus_set_default_dpm_table()
473 memcpy(smu_dpm->golden_dpm_context, dpm_table, in arcturus_set_default_dpm_table()
539 struct arcturus_dpm_table *dpm_table = NULL; in arcturus_populate_umd_state_clk() local
543 dpm_table = smu_dpm->dpm_context; in arcturus_populate_umd_state_clk()
544 gfx_table = &(dpm_table->gfx_table); in arcturus_populate_umd_state_clk()
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/Linux-v5.4/drivers/gpu/drm/amd/powerplay/smumgr/
Dfiji_smumgr.c492 SMU73_Discrete_DpmTable *dpm_table = &(smu_data->smc_state_table); in fiji_populate_bapm_parameters_in_dpm_table() local
504 dpm_table->DefaultTdp = PP_HOST_TO_SMC_US( in fiji_populate_bapm_parameters_in_dpm_table()
506 dpm_table->TargetTdp = PP_HOST_TO_SMC_US( in fiji_populate_bapm_parameters_in_dpm_table()
513 dpm_table->GpuTjMax = (uint8_t)(cac_dtp_table->usTargetOperatingTemp); in fiji_populate_bapm_parameters_in_dpm_table()
514 dpm_table->GpuTjHyst = 8; in fiji_populate_bapm_parameters_in_dpm_table()
516 dpm_table->DTEAmbientTempBase = defaults->DTEAmbientTempBase; in fiji_populate_bapm_parameters_in_dpm_table()
519 dpm_table->TemperatureLimitEdge = PP_HOST_TO_SMC_US( in fiji_populate_bapm_parameters_in_dpm_table()
521 dpm_table->TemperatureLimitHotspot = PP_HOST_TO_SMC_US( in fiji_populate_bapm_parameters_in_dpm_table()
523 dpm_table->TemperatureLimitLiquid1 = PP_HOST_TO_SMC_US( in fiji_populate_bapm_parameters_in_dpm_table()
525 dpm_table->TemperatureLimitLiquid2 = PP_HOST_TO_SMC_US( in fiji_populate_bapm_parameters_in_dpm_table()
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Diceland_smumgr.c767 struct smu7_dpm_table *dpm_table = &data->dpm_table; in iceland_populate_smc_link_level() local
772 for (i = 0; i <= dpm_table->pcie_speed_table.count; i++) { in iceland_populate_smc_link_level()
774 (uint8_t)dpm_table->pcie_speed_table.dpm_levels[i].value; in iceland_populate_smc_link_level()
776 (uint8_t)encode_pcie_lane_width(dpm_table->pcie_speed_table.dpm_levels[i].param1); in iceland_populate_smc_link_level()
788 (uint8_t)dpm_table->pcie_speed_table.count; in iceland_populate_smc_link_level()
790 phm_get_dpm_level_enable_mask_value(&dpm_table->pcie_speed_table); in iceland_populate_smc_link_level()
963 struct smu7_dpm_table *dpm_table = &data->dpm_table; in iceland_populate_all_graphic_levels() local
980 for (i = 0; i < dpm_table->sclk_table.count; i++) { in iceland_populate_all_graphic_levels()
982 dpm_table->sclk_table.dpm_levels[i].value, in iceland_populate_all_graphic_levels()
996 if (dpm_table->sclk_table.count > 1) in iceland_populate_all_graphic_levels()
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Dci_smumgr.c474 struct smu7_dpm_table *dpm_table = &data->dpm_table; in ci_populate_all_graphic_levels() local
484 for (i = 0; i < dpm_table->sclk_table.count; i++) { in ci_populate_all_graphic_levels()
486 dpm_table->sclk_table.dpm_levels[i].value, in ci_populate_all_graphic_levels()
492 if (i == (dpm_table->sclk_table.count - 1)) in ci_populate_all_graphic_levels()
499 smu_data->smc_state_table.GraphicsDpmLevelCount = (u8)dpm_table->sclk_table.count; in ci_populate_all_graphic_levels()
501 phm_get_dpm_level_enable_mask_value(&dpm_table->sclk_table); in ci_populate_all_graphic_levels()
718 SMU7_Discrete_DpmTable *dpm_table = &(smu_data->smc_state_table); in ci_populate_bapm_parameters_in_dpm_table() local
724 dpm_table->DefaultTdp = PP_HOST_TO_SMC_US((uint16_t)(cac_dtp_table->usTDP * 256)); in ci_populate_bapm_parameters_in_dpm_table()
725 dpm_table->TargetTdp = PP_HOST_TO_SMC_US((uint16_t)(cac_dtp_table->usConfigurableTDP * 256)); in ci_populate_bapm_parameters_in_dpm_table()
727 dpm_table->DTETjOffset = 0; in ci_populate_bapm_parameters_in_dpm_table()
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Dvegam_smumgr.c573 struct smu7_dpm_table *dpm_table = &data->dpm_table; in vegam_populate_smc_link_level() local
578 for (i = 0; i <= dpm_table->pcie_speed_table.count; i++) { in vegam_populate_smc_link_level()
580 (uint8_t)dpm_table->pcie_speed_table.dpm_levels[i].value; in vegam_populate_smc_link_level()
582 dpm_table->pcie_speed_table.dpm_levels[i].param1); in vegam_populate_smc_link_level()
590 (uint8_t)dpm_table->pcie_speed_table.count; in vegam_populate_smc_link_level()
594 phm_get_dpm_level_enable_mask_value(&dpm_table->pcie_speed_table); in vegam_populate_smc_link_level()
865 struct smu7_dpm_table *dpm_table = &hw_data->dpm_table; in vegam_populate_all_graphic_levels() local
869 uint8_t pcie_entry_cnt = (uint8_t) hw_data->dpm_table.pcie_speed_table.count; in vegam_populate_all_graphic_levels()
885 for (i = 0; i < dpm_table->sclk_table.count; i++) { in vegam_populate_all_graphic_levels()
888 dpm_table->sclk_table.dpm_levels[i].value, in vegam_populate_all_graphic_levels()
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Dtonga_smumgr.c510 struct smu7_dpm_table *dpm_table = &data->dpm_table; in tonga_populate_smc_link_level() local
515 for (i = 0; i <= dpm_table->pcie_speed_table.count; i++) { in tonga_populate_smc_link_level()
517 (uint8_t)dpm_table->pcie_speed_table.dpm_levels[i].value; in tonga_populate_smc_link_level()
519 (uint8_t)encode_pcie_lane_width(dpm_table->pcie_speed_table.dpm_levels[i].param1); in tonga_populate_smc_link_level()
531 (uint8_t)dpm_table->pcie_speed_table.count; in tonga_populate_smc_link_level()
533 phm_get_dpm_level_enable_mask_value(&dpm_table->pcie_speed_table); in tonga_populate_smc_link_level()
691 struct smu7_dpm_table *dpm_table = &data->dpm_table; in tonga_populate_all_graphic_levels() local
693 uint8_t pcie_entry_count = (uint8_t) data->dpm_table.pcie_speed_table.count; in tonga_populate_all_graphic_levels()
710 for (i = 0; i < dpm_table->sclk_table.count; i++) { in tonga_populate_all_graphic_levels()
712 dpm_table->sclk_table.dpm_levels[i].value, in tonga_populate_all_graphic_levels()
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Dpolaris10_smumgr.c771 struct smu7_dpm_table *dpm_table = &data->dpm_table; in polaris10_populate_smc_link_level() local
776 for (i = 0; i <= dpm_table->pcie_speed_table.count; i++) { in polaris10_populate_smc_link_level()
778 (uint8_t)dpm_table->pcie_speed_table.dpm_levels[i].value; in polaris10_populate_smc_link_level()
780 dpm_table->pcie_speed_table.dpm_levels[i].param1); in polaris10_populate_smc_link_level()
788 (uint8_t)dpm_table->pcie_speed_table.count; in polaris10_populate_smc_link_level()
792 phm_get_dpm_level_enable_mask_value(&dpm_table->pcie_speed_table); in polaris10_populate_smc_link_level()
981 struct smu7_dpm_table *dpm_table = &hw_data->dpm_table; in polaris10_populate_all_graphic_levels() local
985 uint8_t pcie_entry_cnt = (uint8_t) hw_data->dpm_table.pcie_speed_table.count; in polaris10_populate_all_graphic_levels()
1001 for (i = 0; i < dpm_table->sclk_table.count; i++) { in polaris10_populate_all_graphic_levels()
1004 dpm_table->sclk_table.dpm_levels[i].value, in polaris10_populate_all_graphic_levels()
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/Linux-v5.4/drivers/gpu/drm/radeon/
Dci_dpm.c435 SMU7_Discrete_DpmTable *dpm_table = &pi->smc_state_table; in ci_populate_bapm_parameters_in_dpm_table() local
443 dpm_table->DefaultTdp = cac_tdp_table->tdp * 256; in ci_populate_bapm_parameters_in_dpm_table()
444 dpm_table->TargetTdp = cac_tdp_table->configurable_tdp * 256; in ci_populate_bapm_parameters_in_dpm_table()
446 dpm_table->DTETjOffset = (u8)pi->dte_tj_offset; in ci_populate_bapm_parameters_in_dpm_table()
447 dpm_table->GpuTjMax = in ci_populate_bapm_parameters_in_dpm_table()
449 dpm_table->GpuTjHyst = 8; in ci_populate_bapm_parameters_in_dpm_table()
451 dpm_table->DTEAmbientTempBase = pt_defaults->dte_ambient_temp_base; in ci_populate_bapm_parameters_in_dpm_table()
454 dpm_table->PPM_PkgPwrLimit = cpu_to_be16((u16)ppm->dgpu_tdp * 256 / 1000); in ci_populate_bapm_parameters_in_dpm_table()
455 dpm_table->PPM_TemperatureLimit = cpu_to_be16((u16)ppm->tj_max * 256); in ci_populate_bapm_parameters_in_dpm_table()
457 dpm_table->PPM_PkgPwrLimit = cpu_to_be16(0); in ci_populate_bapm_parameters_in_dpm_table()
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Dci_dpm.h195 struct ci_dpm_table dpm_table; member