435 	SMU7_Discrete_DpmTable  *dpm_table = &pi->smc_state_table;  in ci_populate_bapm_parameters_in_dpm_table()  local
443 	dpm_table->DefaultTdp = cac_tdp_table->tdp * 256;  in ci_populate_bapm_parameters_in_dpm_table()
444 	dpm_table->TargetTdp = cac_tdp_table->configurable_tdp * 256;  in ci_populate_bapm_parameters_in_dpm_table()
446 	dpm_table->DTETjOffset = (u8)pi->dte_tj_offset;  in ci_populate_bapm_parameters_in_dpm_table()
447 	dpm_table->GpuTjMax =  in ci_populate_bapm_parameters_in_dpm_table()
449 	dpm_table->GpuTjHyst = 8;  in ci_populate_bapm_parameters_in_dpm_table()
451 	dpm_table->DTEAmbientTempBase = pt_defaults->dte_ambient_temp_base;  in ci_populate_bapm_parameters_in_dpm_table()
454 		dpm_table->PPM_PkgPwrLimit = cpu_to_be16((u16)ppm->dgpu_tdp * 256 / 1000);  in ci_populate_bapm_parameters_in_dpm_table()
455 		dpm_table->PPM_TemperatureLimit = cpu_to_be16((u16)ppm->tj_max * 256);  in ci_populate_bapm_parameters_in_dpm_table()
457 		dpm_table->PPM_PkgPwrLimit = cpu_to_be16(0);  in ci_populate_bapm_parameters_in_dpm_table()
458 		dpm_table->PPM_TemperatureLimit = cpu_to_be16(0);  in ci_populate_bapm_parameters_in_dpm_table()
461 	dpm_table->BAPM_TEMP_GRADIENT = cpu_to_be32(pt_defaults->bapm_temp_gradient);  in ci_populate_bapm_parameters_in_dpm_table()
468 				dpm_table->BAPMTI_R[i][j][k] = cpu_to_be16(*def1);  in ci_populate_bapm_parameters_in_dpm_table()
469 				dpm_table->BAPMTI_RC[i][j][k] = cpu_to_be16(*def2);  in ci_populate_bapm_parameters_in_dpm_table()
2555 	for (i = 0; i < pi->dpm_table.sclk_table.count; i++) {  in ci_do_program_memory_timing_parameters()
2556 		for (j = 0; j < pi->dpm_table.mclk_table.count; j++) {  in ci_do_program_memory_timing_parameters()
2558 								   pi->dpm_table.sclk_table.dpm_levels[i].value,  in ci_do_program_memory_timing_parameters()
2559 								   pi->dpm_table.mclk_table.dpm_levels[j].value,  in ci_do_program_memory_timing_parameters()
2610 static u32 ci_get_dpm_level_enable_mask_value(struct ci_single_dpm_table *dpm_table)  in ci_get_dpm_level_enable_mask_value()  argument
2615 	for (i = dpm_table->count; i > 0; i--) {  in ci_get_dpm_level_enable_mask_value()
2617 		if (dpm_table->dpm_levels[i-1].enabled)  in ci_get_dpm_level_enable_mask_value()
2630 	struct ci_dpm_table *dpm_table = &pi->dpm_table;  in ci_populate_smc_link_level()  local
2633 	for (i = 0; i < dpm_table->pcie_speed_table.count; i++) {  in ci_populate_smc_link_level()
2635 			(u8)dpm_table->pcie_speed_table.dpm_levels[i].value;  in ci_populate_smc_link_level()
2637 			r600_encode_pci_lane_width(dpm_table->pcie_speed_table.dpm_levels[i].param1);  in ci_populate_smc_link_level()
2643 	pi->smc_state_table.LinkLevelCount = (u8)dpm_table->pcie_speed_table.count;  in ci_populate_smc_link_level()
2645 		ci_get_dpm_level_enable_mask_value(&dpm_table->pcie_speed_table);  in ci_populate_smc_link_level()
3279 	struct ci_dpm_table *dpm_table = &pi->dpm_table;  in ci_populate_all_graphic_levels()  local
3289 	for (i = 0; i < dpm_table->sclk_table.count; i++) {  in ci_populate_all_graphic_levels()
3291 						       dpm_table->sclk_table.dpm_levels[i].value,  in ci_populate_all_graphic_levels()
3298 		if (i == (dpm_table->sclk_table.count - 1))  in ci_populate_all_graphic_levels()
3304 	pi->smc_state_table.GraphicsDpmLevelCount = (u8)dpm_table->sclk_table.count;  in ci_populate_all_graphic_levels()
3306 		ci_get_dpm_level_enable_mask_value(&dpm_table->sclk_table);  in ci_populate_all_graphic_levels()
3326 	struct ci_dpm_table *dpm_table = &pi->dpm_table;  in ci_populate_all_memory_levels()  local
3336 	for (i = 0; i < dpm_table->mclk_table.count; i++) {  in ci_populate_all_memory_levels()
3337 		if (dpm_table->mclk_table.dpm_levels[i].value == 0)  in ci_populate_all_memory_levels()
3340 						      dpm_table->mclk_table.dpm_levels[i].value,  in ci_populate_all_memory_levels()
3348 	if ((dpm_table->mclk_table.count >= 2) &&  in ci_populate_all_memory_levels()
3358 	pi->smc_state_table.MemoryDpmLevelCount = (u8)dpm_table->mclk_table.count;  in ci_populate_all_memory_levels()
3360 		ci_get_dpm_level_enable_mask_value(&dpm_table->mclk_table);  in ci_populate_all_memory_levels()
3362 	pi->smc_state_table.MemoryLevel[dpm_table->mclk_table.count - 1].DisplayWatermark =  in ci_populate_all_memory_levels()
3375 				      struct ci_single_dpm_table* dpm_table,  in ci_reset_single_dpm_table()  argument
3380 	dpm_table->count = count;  in ci_reset_single_dpm_table()
3382 		dpm_table->dpm_levels[i].enabled = false;  in ci_reset_single_dpm_table()
3385 static void ci_setup_pcie_table_entry(struct ci_single_dpm_table* dpm_table,  in ci_setup_pcie_table_entry()  argument
3388 	dpm_table->dpm_levels[index].value = pcie_gen;  in ci_setup_pcie_table_entry()
3389 	dpm_table->dpm_levels[index].param1 = pcie_lanes;  in ci_setup_pcie_table_entry()
3390 	dpm_table->dpm_levels[index].enabled = true;  in ci_setup_pcie_table_entry()
3409 				  &pi->dpm_table.pcie_speed_table,  in ci_setup_default_pcie_tables()
3413 		ci_setup_pcie_table_entry(&pi->dpm_table.pcie_speed_table, 0,  in ci_setup_default_pcie_tables()
3417 		ci_setup_pcie_table_entry(&pi->dpm_table.pcie_speed_table, 0,  in ci_setup_default_pcie_tables()
3420 	ci_setup_pcie_table_entry(&pi->dpm_table.pcie_speed_table, 1,  in ci_setup_default_pcie_tables()
3423 	ci_setup_pcie_table_entry(&pi->dpm_table.pcie_speed_table, 2,  in ci_setup_default_pcie_tables()
3426 	ci_setup_pcie_table_entry(&pi->dpm_table.pcie_speed_table, 3,  in ci_setup_default_pcie_tables()
3429 	ci_setup_pcie_table_entry(&pi->dpm_table.pcie_speed_table, 4,  in ci_setup_default_pcie_tables()
3432 	ci_setup_pcie_table_entry(&pi->dpm_table.pcie_speed_table, 5,  in ci_setup_default_pcie_tables()
3436 	pi->dpm_table.pcie_speed_table.count = 6;  in ci_setup_default_pcie_tables()
3461 	memset(&pi->dpm_table, 0, sizeof(struct ci_dpm_table));  in ci_setup_default_dpm_tables()
3464 				  &pi->dpm_table.sclk_table,  in ci_setup_default_dpm_tables()
3467 				  &pi->dpm_table.mclk_table,  in ci_setup_default_dpm_tables()
3470 				  &pi->dpm_table.vddc_table,  in ci_setup_default_dpm_tables()
3473 				  &pi->dpm_table.vddci_table,  in ci_setup_default_dpm_tables()
3476 				  &pi->dpm_table.mvdd_table,  in ci_setup_default_dpm_tables()
3479 	pi->dpm_table.sclk_table.count = 0;  in ci_setup_default_dpm_tables()
3482 		    (pi->dpm_table.sclk_table.dpm_levels[pi->dpm_table.sclk_table.count-1].value !=  in ci_setup_default_dpm_tables()
3484 			pi->dpm_table.sclk_table.dpm_levels[pi->dpm_table.sclk_table.count].value =  in ci_setup_default_dpm_tables()
3486 			pi->dpm_table.sclk_table.dpm_levels[pi->dpm_table.sclk_table.count].enabled =  in ci_setup_default_dpm_tables()
3488 			pi->dpm_table.sclk_table.count++;  in ci_setup_default_dpm_tables()
3492 	pi->dpm_table.mclk_table.count = 0;  in ci_setup_default_dpm_tables()
3495 		    (pi->dpm_table.mclk_table.dpm_levels[pi->dpm_table.mclk_table.count-1].value !=  in ci_setup_default_dpm_tables()
3497 			pi->dpm_table.mclk_table.dpm_levels[pi->dpm_table.mclk_table.count].value =  in ci_setup_default_dpm_tables()
3499 			pi->dpm_table.mclk_table.dpm_levels[pi->dpm_table.mclk_table.count].enabled =  in ci_setup_default_dpm_tables()
3501 			pi->dpm_table.mclk_table.count++;  in ci_setup_default_dpm_tables()
3506 		pi->dpm_table.vddc_table.dpm_levels[i].value =  in ci_setup_default_dpm_tables()
3508 		pi->dpm_table.vddc_table.dpm_levels[i].param1 =  in ci_setup_default_dpm_tables()
3510 		pi->dpm_table.vddc_table.dpm_levels[i].enabled = true;  in ci_setup_default_dpm_tables()
3512 	pi->dpm_table.vddc_table.count = allowed_sclk_vddc_table->count;  in ci_setup_default_dpm_tables()
3517 			pi->dpm_table.vddci_table.dpm_levels[i].value =  in ci_setup_default_dpm_tables()
3519 			pi->dpm_table.vddci_table.dpm_levels[i].enabled = true;  in ci_setup_default_dpm_tables()
3521 		pi->dpm_table.vddci_table.count = allowed_mclk_table->count;  in ci_setup_default_dpm_tables()
3527 			pi->dpm_table.mvdd_table.dpm_levels[i].value =  in ci_setup_default_dpm_tables()
3529 			pi->dpm_table.mvdd_table.dpm_levels[i].enabled = true;  in ci_setup_default_dpm_tables()
3531 		pi->dpm_table.mvdd_table.count = allowed_mclk_table->count;  in ci_setup_default_dpm_tables()
3629 	ret = ci_find_boot_level(&pi->dpm_table.sclk_table,  in ci_init_smc_table()
3633 	ret = ci_find_boot_level(&pi->dpm_table.mclk_table,  in ci_init_smc_table()
3666 	table->PCIeBootLinkLevel = pi->dpm_table.pcie_speed_table.count - 1;  in ci_init_smc_table()
3704 				      struct ci_single_dpm_table *dpm_table,  in ci_trim_single_dpm_states()  argument
3709 	for (i = 0; i < dpm_table->count; i++) {  in ci_trim_single_dpm_states()
3710 		if ((dpm_table->dpm_levels[i].value < low_limit) ||  in ci_trim_single_dpm_states()
3711 		    (dpm_table->dpm_levels[i].value > high_limit))  in ci_trim_single_dpm_states()
3712 			dpm_table->dpm_levels[i].enabled = false;  in ci_trim_single_dpm_states()
3714 			dpm_table->dpm_levels[i].enabled = true;  in ci_trim_single_dpm_states()
3723 	struct ci_single_dpm_table *pcie_table = &pi->dpm_table.pcie_speed_table;  in ci_trim_pcie_dpm_states()
3765 				  &pi->dpm_table.sclk_table,  in ci_trim_dpm_states()
3770 				  &pi->dpm_table.mclk_table,  in ci_trim_dpm_states()
3860 	struct ci_single_dpm_table *sclk_table = &pi->dpm_table.sclk_table;  in ci_find_dpm_states_clocks_in_dpm_table()
3862 	struct ci_single_dpm_table *mclk_table = &pi->dpm_table.mclk_table;  in ci_find_dpm_states_clocks_in_dpm_table()
3904 	struct ci_dpm_table *dpm_table = &pi->dpm_table;  in ci_populate_and_upload_sclk_mclk_dpm_levels()  local
3911 		dpm_table->sclk_table.dpm_levels[dpm_table->sclk_table.count-1].value = sclk;  in ci_populate_and_upload_sclk_mclk_dpm_levels()
3914 		dpm_table->mclk_table.dpm_levels[dpm_table->mclk_table.count-1].value = mclk;  in ci_populate_and_upload_sclk_mclk_dpm_levels()
4179 		ci_get_dpm_level_enable_mask_value(&pi->dpm_table.sclk_table);  in ci_generate_dpm_level_enable_mask()
4181 		ci_get_dpm_level_enable_mask_value(&pi->dpm_table.mclk_table);  in ci_generate_dpm_level_enable_mask()
4189 		ci_get_dpm_level_enable_mask_value(&pi->dpm_table.pcie_speed_table);  in ci_generate_dpm_level_enable_mask()
4744 	for (i = 0; i < pi->dpm_table.mclk_table.count; i++)  in ci_convert_mc_reg_table_to_smc()
4746 						     pi->dpm_table.mclk_table.dpm_levels[i].value,  in ci_convert_mc_reg_table_to_smc()
4785 				    pi->dpm_table.mclk_table.count,  in ci_update_and_upload_mc_reg_table()
5678 	SMU7_Discrete_DpmTable  *dpm_table;  in ci_dpm_init()  local
5827 	dpm_table = &pi->smc_state_table;  in ci_dpm_init()
5831 		dpm_table->VRHotGpio = gpio.shift;  in ci_dpm_init()
5834 		dpm_table->VRHotGpio = CISLANDS_UNUSED_GPIO_PIN;  in ci_dpm_init()
5840 		dpm_table->AcDcGpio = gpio.shift;  in ci_dpm_init()
5843 		dpm_table->AcDcGpio = CISLANDS_UNUSED_GPIO_PIN;  in ci_dpm_init()