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Searched refs:ccu (Results 1 – 25 of 48) sorted by relevance

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/Linux-v5.4/drivers/clk/bcm/
Dclk-kona.c130 static inline u32 __ccu_read(struct ccu_data *ccu, u32 reg_offset) in __ccu_read() argument
132 return readl(ccu->base + reg_offset); in __ccu_read()
137 __ccu_write(struct ccu_data *ccu, u32 reg_offset, u32 reg_val) in __ccu_write() argument
139 writel(reg_val, ccu->base + reg_offset); in __ccu_write()
142 static inline unsigned long ccu_lock(struct ccu_data *ccu) in ccu_lock() argument
146 spin_lock_irqsave(&ccu->lock, flags); in ccu_lock()
150 static inline void ccu_unlock(struct ccu_data *ccu, unsigned long flags) in ccu_unlock() argument
152 spin_unlock_irqrestore(&ccu->lock, flags); in ccu_unlock()
159 static inline void __ccu_write_enable(struct ccu_data *ccu) in __ccu_write_enable() argument
161 if (ccu->write_enabled) { in __ccu_write_enable()
[all …]
Dclk-kona-setup.c26 static bool ccu_data_offsets_valid(struct ccu_data *ccu) in ccu_data_offsets_valid() argument
28 struct ccu_policy *ccu_policy = &ccu->policy; in ccu_data_offsets_valid()
31 limit = ccu->range - sizeof(u32); in ccu_data_offsets_valid()
37 ccu->name, ccu_policy->enable.offset, limit); in ccu_data_offsets_valid()
43 ccu->name, ccu_policy->control.offset, limit); in ccu_data_offsets_valid()
93 range = bcm_clk->ccu->range; in peri_clk_data_offsets_valid()
747 static void ccu_clks_teardown(struct ccu_data *ccu) in ccu_clks_teardown() argument
751 for (i = 0; i < ccu->clk_num; i++) in ccu_clks_teardown()
752 kona_clk_teardown(&ccu->kona_clks[i].hw); in ccu_clks_teardown()
755 static void kona_ccu_teardown(struct ccu_data *ccu) in kona_ccu_teardown() argument
[all …]
/Linux-v5.4/arch/arm/boot/dts/
Dsunxi-h3-h5.dtsi44 #include <dt-bindings/clock/sun8i-h3-ccu.h>
45 #include <dt-bindings/clock/sun8i-r-ccu.h>
48 #include <dt-bindings/reset/sun8i-h3-ccu.h>
49 #include <dt-bindings/reset/sun8i-r-ccu.h>
66 <&ccu CLK_TCON0>, <&ccu CLK_HDMI>;
75 <&ccu CLK_TVE>;
117 clocks = <&ccu CLK_BUS_DE>,
118 <&ccu CLK_DE>;
121 resets = <&ccu RST_BUS_DE>;
153 clocks = <&ccu CLK_BUS_DMA>;
[all …]
Dsun6i-a31.dtsi48 #include <dt-bindings/clock/sun6i-a31-ccu.h>
49 #include <dt-bindings/reset/sun6i-a31-ccu.h>
69 clocks = <&ccu CLK_AHB1_BE0>, <&ccu CLK_AHB1_LCD0>,
70 <&ccu CLK_AHB1_HDMI>, <&ccu CLK_DRAM_BE0>,
71 <&ccu CLK_IEP_DRC0>, <&ccu CLK_BE0>,
72 <&ccu CLK_LCD0_CH1>, <&ccu CLK_HDMI>;
80 clocks = <&ccu CLK_AHB1_BE0>, <&ccu CLK_AHB1_LCD0>,
81 <&ccu CLK_DRAM_BE0>, <&ccu CLK_IEP_DRC0>,
82 <&ccu CLK_BE0>, <&ccu CLK_LCD0_CH0>;
106 clocks = <&ccu CLK_CPU>;
[all …]
Dsun4i-a10.dtsi46 #include <dt-bindings/clock/sun4i-a10-ccu.h>
47 #include <dt-bindings/reset/sun4i-a10-ccu.h>
67 clocks = <&ccu CLK_AHB_LCD0>, <&ccu CLK_AHB_HDMI0>,
68 <&ccu CLK_AHB_DE_BE0>, <&ccu CLK_DE_BE0>,
69 <&ccu CLK_TCON0_CH1>, <&ccu CLK_DRAM_DE_BE0>;
77 clocks = <&ccu CLK_AHB_LCD0>, <&ccu CLK_AHB_HDMI0>,
78 <&ccu CLK_AHB_DE_BE0>, <&ccu CLK_AHB_DE_FE0>,
79 <&ccu CLK_DE_BE0>, <&ccu CLK_DE_FE0>,
80 <&ccu CLK_TCON0_CH1>, <&ccu CLK_HDMI>,
81 <&ccu CLK_DRAM_DE_FE0>, <&ccu CLK_DRAM_DE_BE0>;
[all …]
Dsun8i-r40.dtsi46 #include <dt-bindings/clock/sun8i-r40-ccu.h>
47 #include <dt-bindings/reset/sun8i-r40-ccu.h>
122 clocks = <&ccu CLK_BUS_DE>,
123 <&ccu CLK_DE>;
126 resets = <&ccu RST_BUS_DE>;
187 clocks = <&ccu CLK_BUS_MMC0>, <&ccu CLK_MMC0>;
189 resets = <&ccu RST_BUS_MMC0>;
203 clocks = <&ccu CLK_BUS_MMC1>, <&ccu CLK_MMC1>;
205 resets = <&ccu RST_BUS_MMC1>;
217 clocks = <&ccu CLK_BUS_MMC2>, <&ccu CLK_MMC2>;
[all …]
Dsun8i-a83t.dtsi47 #include <dt-bindings/clock/sun8i-a83t-ccu.h>
49 #include <dt-bindings/clock/sun8i-r-ccu.h>
50 #include <dt-bindings/reset/sun8i-a83t-ccu.h>
52 #include <dt-bindings/reset/sun8i-r-ccu.h>
66 clocks = <&ccu CLK_C0CPUX>;
77 clocks = <&ccu CLK_C0CPUX>;
88 clocks = <&ccu CLK_C0CPUX>;
99 clocks = <&ccu CLK_C0CPUX>;
110 clocks = <&ccu CLK_C1CPUX>;
121 clocks = <&ccu CLK_C1CPUX>;
[all …]
Dsun8i-v3s.dtsi44 #include <dt-bindings/clock/sun8i-v3s-ccu.h>
45 #include <dt-bindings/reset/sun8i-v3s-ccu.h>
60 clocks = <&ccu CLK_CPU>;
109 clocks = <&ccu CLK_BUS_DE>,
110 <&ccu CLK_DE>;
113 resets = <&ccu RST_BUS_DE>;
147 clocks = <&ccu CLK_BUS_TCON0>,
148 <&ccu CLK_TCON0>;
153 resets = <&ccu RST_BUS_TCON0>;
181 clocks = <&ccu CLK_BUS_MMC0>,
[all …]
Dsun7i-a20.dtsi48 #include <dt-bindings/clock/sun7i-a20-ccu.h>
49 #include <dt-bindings/reset/sun4i-a10-ccu.h>
69 clocks = <&ccu CLK_AHB_LCD0>, <&ccu CLK_AHB_HDMI0>,
70 <&ccu CLK_AHB_DE_BE0>, <&ccu CLK_DE_BE0>,
71 <&ccu CLK_TCON0_CH1>, <&ccu CLK_DRAM_DE_BE0>,
72 <&ccu CLK_HDMI>;
80 clocks = <&ccu CLK_AHB_LCD0>, <&ccu CLK_AHB_DE_BE0>,
81 <&ccu CLK_DE_BE0>, <&ccu CLK_TCON0_CH0>,
82 <&ccu CLK_DRAM_DE_BE0>;
90 clocks = <&ccu CLK_AHB_TVE0>, <&ccu CLK_AHB_LCD0>,
[all …]
Dsun5i.dtsi45 #include <dt-bindings/clock/sun5i-ccu.h>
47 #include <dt-bindings/reset/sun5i-ccu.h>
62 clocks = <&ccu CLK_CPU>;
75 clocks = <&ccu CLK_AHB_LCD>, <&ccu CLK_AHB_DE_BE>, <&ccu CLK_DE_BE>,
76 <&ccu CLK_TCON_CH0>, <&ccu CLK_DRAM_DE_BE>;
84 clocks = <&ccu CLK_AHB_TVE>, <&ccu CLK_AHB_LCD>,
85 <&ccu CLK_AHB_DE_BE>, <&ccu CLK_DE_BE>,
86 <&ccu CLK_TCON_CH1>, <&ccu CLK_DRAM_DE_BE>;
188 clocks = <&ccu 99>;
197 clocks = <&ccu CLK_AHB_DMA>;
[all …]
Dsun8i-a23-a33.dtsi47 #include <dt-bindings/clock/sun8i-a23-a33-ccu.h>
48 #include <dt-bindings/reset/sun8i-a23-a33-ccu.h>
64 clocks = <&ccu CLK_BUS_LCD>, <&ccu CLK_BUS_DE_BE>,
65 <&ccu CLK_LCD_CH0>, <&ccu CLK_DE_BE>,
66 <&ccu CLK_DRAM_DE_BE>, <&ccu CLK_DRC>;
159 clocks = <&ccu CLK_BUS_DMA>;
160 resets = <&ccu RST_BUS_DMA>;
168 clocks = <&ccu CLK_BUS_NAND>, <&ccu CLK_NAND>;
170 resets = <&ccu RST_BUS_NAND>;
185 clocks = <&ccu CLK_BUS_LCD>,
[all …]
Dsun8i-h3.dtsi77 clocks = <&ccu CLK_CPUX>;
87 clocks = <&ccu CLK_CPUX>;
97 clocks = <&ccu CLK_CPUX>;
107 clocks = <&ccu CLK_CPUX>;
148 clocks = <&ccu CLK_BUS_VE>, <&ccu CLK_VE>,
149 <&ccu CLK_DRAM_VE>;
151 resets = <&ccu RST_BUS_VE>;
173 clocks = <&ccu CLK_BUS_GPU>, <&ccu CLK_GPU>;
175 resets = <&ccu RST_BUS_GPU>;
177 assigned-clocks = <&ccu CLK_GPU>;
[all …]
Dsun8i-a33.dtsi128 clocks = <&ccu CLK_CPUX>;
135 clocks = <&ccu CLK_CPUX>;
145 clocks = <&ccu CLK_CPUX>;
155 clocks = <&ccu CLK_CPUX>;
209 clocks = <&ccu CLK_BUS_VE>, <&ccu CLK_VE>,
210 <&ccu CLK_DRAM_VE>;
212 resets = <&ccu RST_BUS_VE>;
221 clocks = <&ccu CLK_BUS_SS>, <&ccu CLK_SS>;
223 resets = <&ccu RST_BUS_SS>;
232 clocks = <&ccu CLK_BUS_CODEC>, <&ccu CLK_AC_DIG>;
[all …]
Dsun9i-a80.dtsi47 #include <dt-bindings/clock/sun9i-a80-ccu.h>
50 #include <dt-bindings/reset/sun9i-a80-ccu.h>
226 <&ccu CLK_PLL_PERIPH0>,
227 <&ccu CLK_PLL_AUDIO>;
326 clocks = <&ccu CLK_BUS_GMAC>, <&gmac_tx_clk>;
328 resets = <&ccu RST_BUS_GMAC>;
449 clocks = <&ccu CLK_BUS_USB>, <&osc24M>;
463 clocks = <&mmc_config_clk 0>, <&ccu CLK_MMC0>,
464 <&ccu CLK_MMC0_OUTPUT>,
465 <&ccu CLK_MMC0_SAMPLE>;
[all …]
Dsuniv-f1c100s.dtsi65 ccu: clock@1c20000 { label
66 compatible = "allwinner,suniv-f1c100s-ccu";
85 clocks = <&ccu 37>, <&osc24M>, <&osc32k>;
117 clocks = <&ccu 38>;
118 resets = <&ccu 24>;
128 clocks = <&ccu 39>;
129 resets = <&ccu 25>;
139 clocks = <&ccu 40>;
140 resets = <&ccu 26>;
Dsun5i-a10s.dtsi63 clocks = <&ccu CLK_AHB_LCD>, <&ccu CLK_AHB_HDMI>,
64 <&ccu CLK_AHB_DE_BE>, <&ccu CLK_DRAM_DE_BE>,
65 <&ccu CLK_DE_BE>, <&ccu CLK_HDMI>;
80 clocks = <&ccu CLK_AHB_HDMI>, <&ccu CLK_HDMI>,
81 <&ccu CLK_PLL_VIDEO0_2X>,
82 <&ccu CLK_PLL_VIDEO1_2X>;
111 clocks = <&ccu CLK_HOSC>;
118 &ccu {
119 compatible = "allwinner,sun5i-a10s-ccu";
Dsun5i-gr8.dtsi47 #include <dt-bindings/clock/sun5i-ccu.h>
49 #include <dt-bindings/reset/sun5i-ccu.h>
61 clocks = <&ccu CLK_HOSC>;
71 clocks = <&ccu CLK_APB0_SPDIF>, <&ccu CLK_SPDIF>;
84 clocks = <&ccu CLK_APB0_I2S>, <&ccu CLK_I2S>;
94 &ccu {
95 compatible = "nextthing,gr8-ccu";
/Linux-v5.4/drivers/clk/sunxi-ng/
DMakefile24 obj-$(CONFIG_SUNIV_F1C100S_CCU) += ccu-suniv-f1c100s.o
25 obj-$(CONFIG_SUN50I_A64_CCU) += ccu-sun50i-a64.o
26 obj-$(CONFIG_SUN50I_H6_CCU) += ccu-sun50i-h6.o
27 obj-$(CONFIG_SUN50I_H6_R_CCU) += ccu-sun50i-h6-r.o
28 obj-$(CONFIG_SUN4I_A10_CCU) += ccu-sun4i-a10.o
29 obj-$(CONFIG_SUN5I_CCU) += ccu-sun5i.o
30 obj-$(CONFIG_SUN6I_A31_CCU) += ccu-sun6i-a31.o
31 obj-$(CONFIG_SUN8I_A23_CCU) += ccu-sun8i-a23.o
32 obj-$(CONFIG_SUN8I_A33_CCU) += ccu-sun8i-a33.o
33 obj-$(CONFIG_SUN8I_A83T_CCU) += ccu-sun8i-a83t.o
[all …]
Dccu_reset.c16 struct ccu_reset *ccu = rcdev_to_ccu_reset(rcdev); in ccu_reset_assert() local
17 const struct ccu_reset_map *map = &ccu->reset_map[id]; in ccu_reset_assert()
21 spin_lock_irqsave(ccu->lock, flags); in ccu_reset_assert()
23 reg = readl(ccu->base + map->reg); in ccu_reset_assert()
24 writel(reg & ~map->bit, ccu->base + map->reg); in ccu_reset_assert()
26 spin_unlock_irqrestore(ccu->lock, flags); in ccu_reset_assert()
34 struct ccu_reset *ccu = rcdev_to_ccu_reset(rcdev); in ccu_reset_deassert() local
35 const struct ccu_reset_map *map = &ccu->reset_map[id]; in ccu_reset_deassert()
39 spin_lock_irqsave(ccu->lock, flags); in ccu_reset_deassert()
41 reg = readl(ccu->base + map->reg); in ccu_reset_deassert()
[all …]
/Linux-v5.4/arch/arm64/boot/dts/allwinner/
Dsun50i-h6.dtsi7 #include <dt-bindings/clock/sun50i-h6-ccu.h>
8 #include <dt-bindings/clock/sun50i-h6-r-ccu.h>
11 #include <dt-bindings/reset/sun50i-h6-ccu.h>
12 #include <dt-bindings/reset/sun50i-h6-r-ccu.h>
108 clocks = <&ccu CLK_DE>,
109 <&ccu CLK_BUS_DE>;
112 resets = <&ccu RST_BUS_DE>;
144 clocks = <&ccu CLK_BUS_VE>, <&ccu CLK_VE>,
145 <&ccu CLK_MBUS_VE>;
147 resets = <&ccu RST_BUS_VE>;
[all …]
Dsun50i-a64.dtsi45 #include <dt-bindings/clock/sun50i-a64-ccu.h>
47 #include <dt-bindings/clock/sun8i-r-ccu.h>
49 #include <dt-bindings/reset/sun50i-a64-ccu.h>
51 #include <dt-bindings/reset/sun8i-r-ccu.h>
67 clocks = <&ccu CLK_TCON0>,
77 <&ccu CLK_TCON1>, <&ccu CLK_HDMI>;
222 clocks = <&ccu CLK_BUS_DE>,
223 <&ccu CLK_DE>;
226 resets = <&ccu RST_BUS_DE>;
333 clocks = <&ccu CLK_BUS_DMA>;
[all …]
Dsun50i-h5.dtsi122 clocks = <&ccu CLK_BUS_VE>, <&ccu CLK_VE>,
123 <&ccu CLK_DRAM_VE>;
125 resets = <&ccu RST_BUS_VE>;
163 clocks = <&ccu CLK_BUS_GPU>, <&ccu CLK_GPU>;
165 resets = <&ccu RST_BUS_GPU>;
167 assigned-clocks = <&ccu CLK_GPU>;
173 &ccu {
174 compatible = "allwinner,sun50i-h5-ccu";
184 clocks = <&ccu CLK_BUS_MMC0>, <&ccu CLK_MMC0>;
191 clocks = <&ccu CLK_BUS_MMC1>, <&ccu CLK_MMC1>;
[all …]
/Linux-v5.4/Documentation/devicetree/bindings/clock/
Dbrcm,kona-ccu.txt13 Shall have a value of the form "brcm,<model>-<which>-ccu",
16 "brcm,bcm11351-root-ccu"
32 compatible = "brcm,bcm11351-slave-ccu";
59 "brcm,bcm11351-root-ccu"
60 "brcm,bcm11351-aon-ccu"
61 "brcm,bcm11351-hub-ccu"
62 "brcm,bcm11351-master-ccu"
63 "brcm,bcm11351-slave-ccu"
105 "brcm,bcm21664-root-ccu"
106 "brcm,bcm21664-aon-ccu"
[all …]
Dsun9i-de.txt23 clocks = <&ccu CLK_DE>, <&ccu CLK_SDRAM>, <&ccu CLK_BUS_DE>;
25 resets = <&ccu RST_BUS_DE>;
/Linux-v5.4/Documentation/devicetree/bindings/media/
Dcedrus.txt50 clocks = <&ccu CLK_AHB_VE>, <&ccu CLK_VE>,
51 <&ccu CLK_DRAM_VE>;
54 resets = <&ccu RST_VE>;

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