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Searched refs:num_states (Results 1 – 25 of 34) sorted by relevance

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/Linux-v5.15/arch/powerpc/kernel/
Drtas-proc.c513 int num_states = 0; in ppc_rtas_process_sensor() local
522 num_states = sizeof(key_switch) / sizeof(char *); in ppc_rtas_process_sensor()
523 if (state < num_states) { in ppc_rtas_process_sensor()
530 num_states = sizeof(enclosure_switch) / sizeof(char *); in ppc_rtas_process_sensor()
531 if (state < num_states) { in ppc_rtas_process_sensor()
543 num_states = sizeof(lid_status) / sizeof(char *); in ppc_rtas_process_sensor()
544 if (state < num_states) { in ppc_rtas_process_sensor()
551 num_states = sizeof(power_source) / sizeof(char *); in ppc_rtas_process_sensor()
552 if (state < num_states) { in ppc_rtas_process_sensor()
563 num_states = sizeof(battery_remaining) / sizeof(char *); in ppc_rtas_process_sensor()
[all …]
/Linux-v5.15/drivers/regulator/
Dirq_helpers.c62 num_rdevs = rid->num_states; in regulator_notifier_isr_work()
167 num_rdevs = rid->num_states; in regulator_notifier_isr()
291 h->rdata.num_states = rdev_amount; in init_rdev_state()
308 for (i = 0; i < h->rdata.num_states; i++) in init_rdev_errors()
/Linux-v5.15/drivers/gpu/drm/amd/display/dc/dcn302/
Ddcn302_resource.c166 .num_states = 1,
1281 unsigned int num_states = 0; in dcn302_update_bw_bounding_box() local
1365 while (i < num_dcfclk_sta_targets && j < num_uclk_states && num_states < DC__VOLTAGE_STATES) { in dcn302_update_bw_bounding_box()
1367 dcfclk_mhz[num_states] = dcfclk_sta_targets[i]; in dcn302_update_bw_bounding_box()
1368 dram_speed_mts[num_states++] = optimal_uclk_for_dcfclk_sta_targets[i++]; in dcn302_update_bw_bounding_box()
1371 dcfclk_mhz[num_states] = optimal_dcfclk_for_uclk[j]; in dcn302_update_bw_bounding_box()
1372 dram_speed_mts[num_states++] = bw_params->clk_table.entries[j++].memclk_mhz * 16; in dcn302_update_bw_bounding_box()
1379 while (i < num_dcfclk_sta_targets && num_states < DC__VOLTAGE_STATES) { in dcn302_update_bw_bounding_box()
1380 dcfclk_mhz[num_states] = dcfclk_sta_targets[i]; in dcn302_update_bw_bounding_box()
1381 dram_speed_mts[num_states++] = optimal_uclk_for_dcfclk_sta_targets[i++]; in dcn302_update_bw_bounding_box()
[all …]
/Linux-v5.15/drivers/gpu/drm/amd/display/dc/dcn303/
Ddcn303_resource.c148 .num_states = 1,
1215 unsigned int num_states = 0; in dcn303_update_bw_bounding_box() local
1296 while (i < num_dcfclk_sta_targets && j < num_uclk_states && num_states < DC__VOLTAGE_STATES) { in dcn303_update_bw_bounding_box()
1298 dcfclk_mhz[num_states] = dcfclk_sta_targets[i]; in dcn303_update_bw_bounding_box()
1299 dram_speed_mts[num_states++] = optimal_uclk_for_dcfclk_sta_targets[i++]; in dcn303_update_bw_bounding_box()
1302 dcfclk_mhz[num_states] = optimal_dcfclk_for_uclk[j]; in dcn303_update_bw_bounding_box()
1303 dram_speed_mts[num_states++] = in dcn303_update_bw_bounding_box()
1311 while (i < num_dcfclk_sta_targets && num_states < DC__VOLTAGE_STATES) { in dcn303_update_bw_bounding_box()
1312 dcfclk_mhz[num_states] = dcfclk_sta_targets[i]; in dcn303_update_bw_bounding_box()
1313 dram_speed_mts[num_states++] = optimal_uclk_for_dcfclk_sta_targets[i++]; in dcn303_update_bw_bounding_box()
[all …]
/Linux-v5.15/net/netfilter/ipvs/
Dip_vs_proto_ah_esp.c119 .num_states = 1,
141 .num_states = 1,
Dip_vs_proto_udp.c485 .num_states = IP_VS_UDP_S_LAST,
Dip_vs_proto_sctp.c577 .num_states = IP_VS_SCTP_S_LAST,
/Linux-v5.15/drivers/gpu/drm/amd/display/dc/dcn30/
Ddcn30_resource.c183 .num_states = 1,
1900 if (vlevel < context->bw_ctx.dml.soc.num_states) in dcn30_internal_validate_bw()
1903 if (fast_validate || vlevel == context->bw_ctx.dml.soc.num_states || in dcn30_internal_validate_bw()
1916 if (vlevel < context->bw_ctx.dml.soc.num_states) { in dcn30_internal_validate_bw()
1925 if (vlevel == context->bw_ctx.dml.soc.num_states) in dcn30_internal_validate_bw()
2090 vba->ValidationStatus[vba->soc.num_states] = DML_FAIL_DSC_VALIDATION_FAILURE; in dcn30_internal_validate_bw()
2330 …_status_message(context->bw_ctx.dml.vba.ValidationStatus[context->bw_ctx.dml.vba.soc.num_states])); in dcn30_validate_bandwidth()
2380 unsigned int num_states = 0; in dcn30_update_bw_bounding_box() local
2466 while (i < num_dcfclk_sta_targets && j < num_uclk_states && num_states < DC__VOLTAGE_STATES) { in dcn30_update_bw_bounding_box()
2468 dcfclk_mhz[num_states] = dcfclk_sta_targets[i]; in dcn30_update_bw_bounding_box()
[all …]
/Linux-v5.15/drivers/gpu/drm/amd/display/dc/dcn21/
Ddcn21_resource.c306 .num_states = 8
1044 ASSERT(vlevel < dml->soc.num_states); in calculate_wm_set_for_vlevel()
1218 if (vlevel > context->bw_ctx.dml.soc.num_states) { in dcn21_fast_validate_bw()
1229 if (vlevel > context->bw_ctx.dml.soc.num_states) in dcn21_fast_validate_bw()
1316 context->bw_ctx.dml.vba.ValidationStatus[context->bw_ctx.dml.vba.soc.num_states] = in dcn21_fast_validate_bw()
1375 …_status_message(context->bw_ctx.dml.vba.ValidationStatus[context->bw_ctx.dml.vba.soc.num_states])); in dcn21_validate_bandwidth_fp()
1604 for (i = 0; i < dcn2_1_soc.num_states + 1; i++) { in update_bw_bounding_box()
1610 for (closest_clk_lvl = 0, j = dcn2_1_soc.num_states - 1; j >= 0; j--) { in update_bw_bounding_box()
1640 dcn2_1_soc.num_states = clk_table->num_entries + 1; in update_bw_bounding_box()
1644 …dcn2_1_soc.clock_limits[dcn2_1_soc.num_states] = dcn2_1_soc.clock_limits[dcn2_1_soc.num_states - 1… in update_bw_bounding_box()
[all …]
/Linux-v5.15/drivers/gpu/drm/amd/amdgpu/
Damdgpu_socbb.h78 uint32_t num_states; member
/Linux-v5.15/drivers/gpu/drm/amd/display/dc/dcn301/
Ddcn301_resource.c266 .num_states = 5,
1536 if (loaded_bb->num_states == 1) { in set_wm_ranges()
1544 } else if (loaded_bb->num_states > 1) { in set_wm_ranges()
1545 for (i = 0; i < 4 && i < loaded_bb->num_states; i++) { in set_wm_ranges()
1588 for (closest_clk_lvl = 0, j = dcn3_01_soc.num_states - 1; j >= 0; j--) { in dcn301_update_bw_bounding_box()
1612 dcn3_01_soc.num_states = clk_table->num_entries; in dcn301_update_bw_bounding_box()
1614 …dcn3_01_soc.clock_limits[dcn3_01_soc.num_states] = dcn3_01_soc.clock_limits[dcn3_01_soc.num_states… in dcn301_update_bw_bounding_box()
1615 dcn3_01_soc.clock_limits[dcn3_01_soc.num_states].state = dcn3_01_soc.num_states; in dcn301_update_bw_bounding_box()
/Linux-v5.15/drivers/gpu/drm/amd/display/dc/dcn20/
Ddcn20_resource.c301 .num_states = 5,
412 .num_states = 5,
2687 for (vlevel_split = vlevel; vlevel <= context->bw_ctx.dml.soc.num_states; vlevel++) in dcn20_validate_apply_pipe_split_flags()
2692 if (vlevel > context->bw_ctx.dml.soc.num_states) in dcn20_validate_apply_pipe_split_flags()
2837 if (vlevel > context->bw_ctx.dml.soc.num_states) in dcn20_fast_validate_bw()
2908 context->bw_ctx.dml.vba.ValidationStatus[context->bw_ctx.dml.vba.soc.num_states] = in dcn20_fast_validate_bw()
3199 …_status_message(context->bw_ctx.dml.vba.ValidationStatus[context->bw_ctx.dml.vba.soc.num_states])); in dcn20_validate_bandwidth_internal()
3448 for (i = 0; i < bb->num_states; i++) { in dcn20_cap_soc_clocks()
3483 for (i = bb->num_states - 1; i > 1; i--) { in dcn20_cap_soc_clocks()
3504 bb->num_states--; in dcn20_cap_soc_clocks()
[all …]
Ddcn20_resource.h103 struct pp_smu_nv_clock_table *max_clocks, unsigned int *uclk_states, unsigned int num_states);
/Linux-v5.15/drivers/gpu/drm/amd/display/dc/
Ddm_pp_smu.h229 unsigned int *clock_values_in_khz, unsigned int *num_states);
/Linux-v5.15/drivers/gpu/drm/amd/display/dc/dml/dcn30/
Ddisplay_mode_vba_30.c2056 v->soc.clock_limits[mode_lib->soc.num_states - 1].dispclk_mhz, in DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation()
3957 for (i = 0; i < v->soc.num_states; i++) { in dml30_ModeSupportAndSystemConfigurationFull()
3966 …utODMCombine >= v->MaxDispclk[i] && v->MaxDispclk[i] == v->MaxDispclk[mode_lib->soc.num_states - 1] in dml30_ModeSupportAndSystemConfigurationFull()
3967 && v->MaxDppclk[i] == v->MaxDppclk[mode_lib->soc.num_states - 1])) { in dml30_ModeSupportAndSystemConfigurationFull()
3972 …MCombine2To1 >= v->MaxDispclk[i] && v->MaxDispclk[i] == v->MaxDispclk[mode_lib->soc.num_states - 1] in dml30_ModeSupportAndSystemConfigurationFull()
3973 && v->MaxDppclk[i] == v->MaxDppclk[mode_lib->soc.num_states - 1])) { in dml30_ModeSupportAndSystemConfigurationFull()
3978 …MCombine4To1 >= v->MaxDispclk[i] && v->MaxDispclk[i] == v->MaxDispclk[mode_lib->soc.num_states - 1] in dml30_ModeSupportAndSystemConfigurationFull()
3979 && v->MaxDppclk[i] == v->MaxDppclk[mode_lib->soc.num_states - 1])) { in dml30_ModeSupportAndSystemConfigurationFull()
4087 …(v->MaxDispclk[i] == v->MaxDispclk[v->soc.num_states - 1] && v->MaxDppclk[i] == v->MaxDppclk[v->so… in dml30_ModeSupportAndSystemConfigurationFull()
4113 for (i = 0; i < v->soc.num_states; i++) { in dml30_ModeSupportAndSystemConfigurationFull()
[all …]
/Linux-v5.15/drivers/gpu/drm/amd/display/dc/dml/dcn20/
Ddisplay_mode_vba_20.c1260 mode_lib->vba.soc.clock_limits[mode_lib->vba.soc.num_states].dispclk_mhz, in dml20_DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation()
2598 for (k = 0; k <= mode_lib->vba.soc.num_states; k++) in dml20_DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation()
3441 for (i = 0; i <= mode_lib->vba.soc.num_states; i++) { in dml20_ModeSupportAndSystemConfigurationFull()
3523 for (i = 0; i <= mode_lib->vba.soc.num_states; i++) { in dml20_ModeSupportAndSystemConfigurationFull()
3874 for (i = 0; i <= mode_lib->vba.soc.num_states; i++) { in dml20_ModeSupportAndSystemConfigurationFull()
3889 && i == mode_lib->vba.soc.num_states) in dml20_ModeSupportAndSystemConfigurationFull()
3896 && i == mode_lib->vba.soc.num_states) in dml20_ModeSupportAndSystemConfigurationFull()
3970 if (i != mode_lib->vba.soc.num_states) { in dml20_ModeSupportAndSystemConfigurationFull()
4002 for (i = 0; i <= mode_lib->vba.soc.num_states; i++) { in dml20_ModeSupportAndSystemConfigurationFull()
4019 for (i = 0; i <= mode_lib->vba.soc.num_states; i++) { in dml20_ModeSupportAndSystemConfigurationFull()
[all …]
Ddisplay_mode_vba_20v2.c1320 mode_lib->vba.soc.clock_limits[mode_lib->vba.soc.num_states].dispclk_mhz, in dml20v2_DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation()
2671 for (k = 0; k <= mode_lib->vba.soc.num_states; k++) in dml20v2_DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation()
3548 for (i = 0; i <= mode_lib->vba.soc.num_states; i++) { in dml20v2_ModeSupportAndSystemConfigurationFull()
3630 for (i = 0; i <= mode_lib->vba.soc.num_states; i++) { in dml20v2_ModeSupportAndSystemConfigurationFull()
3981 for (i = 0; i <= mode_lib->vba.soc.num_states; i++) { in dml20v2_ModeSupportAndSystemConfigurationFull()
3983 mode_lib->vba.MaxDispclk[mode_lib->vba.soc.num_states], in dml20v2_ModeSupportAndSystemConfigurationFull()
4000 && i == mode_lib->vba.soc.num_states) in dml20v2_ModeSupportAndSystemConfigurationFull()
4007 && i == mode_lib->vba.soc.num_states) in dml20v2_ModeSupportAndSystemConfigurationFull()
4084 if (i != mode_lib->vba.soc.num_states) { in dml20v2_ModeSupportAndSystemConfigurationFull()
4116 for (i = 0; i <= mode_lib->vba.soc.num_states; i++) { in dml20v2_ModeSupportAndSystemConfigurationFull()
[all …]
/Linux-v5.15/drivers/gpu/drm/amd/display/dc/dml/dcn31/
Ddisplay_mode_vba_31.c2239 v->soc.clock_limits[v->soc.num_states - 1].dispclk_mhz,
4229 for (i = 0; i < v->soc.num_states; i++) {
4239 && v->MaxDispclk[i] == v->MaxDispclk[v->soc.num_states - 1]
4240 && v->MaxDppclk[i] == v->MaxDppclk[v->soc.num_states - 1])) {
4247 && v->MaxDispclk[i] == v->MaxDispclk[v->soc.num_states - 1]
4248 && v->MaxDppclk[i] == v->MaxDppclk[v->soc.num_states - 1])) {
4255 && v->MaxDispclk[i] == v->MaxDispclk[v->soc.num_states - 1]
4256 && v->MaxDppclk[i] == v->MaxDppclk[v->soc.num_states - 1])) {
4383 if (!(v->MaxDispclk[i] == v->MaxDispclk[v->soc.num_states - 1]
4384 && v->MaxDppclk[i] == v->MaxDppclk[v->soc.num_states - 1])) {
[all …]
/Linux-v5.15/drivers/gpu/drm/amd/display/dc/dml/dcn21/
Ddisplay_mode_vba_21.c1642 mode_lib->vba.soc.clock_limits[mode_lib->vba.soc.num_states - 1].dispclk_mhz, in DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation()
3551 for (i = 0; i <= mode_lib->vba.soc.num_states; i++) { in dml21_ModeSupportAndSystemConfigurationFull()
3593 for (i = 0; i <= mode_lib->vba.soc.num_states; i++) { in dml21_ModeSupportAndSystemConfigurationFull()
3947 for (i = 0; i <= mode_lib->vba.soc.num_states; i++) { in dml21_ModeSupportAndSystemConfigurationFull()
3949 mode_lib->vba.MaxDispclk[mode_lib->vba.soc.num_states], in dml21_ModeSupportAndSystemConfigurationFull()
3971 && i == mode_lib->vba.soc.num_states) in dml21_ModeSupportAndSystemConfigurationFull()
3978 && i == mode_lib->vba.soc.num_states) in dml21_ModeSupportAndSystemConfigurationFull()
4055 if (i != mode_lib->vba.soc.num_states) { in dml21_ModeSupportAndSystemConfigurationFull()
4087 for (i = 0; i <= mode_lib->vba.soc.num_states; i++) { in dml21_ModeSupportAndSystemConfigurationFull()
4104 for (i = 0; i <= mode_lib->vba.soc.num_states; i++) { in dml21_ModeSupportAndSystemConfigurationFull()
[all …]
/Linux-v5.15/include/linux/regulator/
Ddriver.h489 int num_states; member
/Linux-v5.15/drivers/gpu/drm/amd/display/dc/dml/
Ddisplay_mode_structs.h74 unsigned int num_states; member
Ddisplay_mode_lib.c266 for (i = mode_lib->vba.soc.num_states; i >= 0; i--) { in dml_log_mode_support_params()
/Linux-v5.15/drivers/gpu/drm/amd/display/amdgpu_dm/
Damdgpu_dm_pp_smu.c775 unsigned int *clock_values_in_khz, unsigned int *num_states) in pp_nv_get_uclk_dpm_states() argument
787 num_states)) in pp_nv_get_uclk_dpm_states()
/Linux-v5.15/drivers/gpu/drm/amd/include/
Dkgd_pp_interface.h395 unsigned int *num_states);
/Linux-v5.15/drivers/gpu/drm/amd/pm/inc/
Damdgpu_smu.h754 int (*get_uclk_dpm_states)(struct smu_context *smu, uint32_t *clocks_in_khz, uint32_t *num_states);

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