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Searched refs:tegra_dc_readl (Results 1 – 7 of 7) sorted by relevance

/Linux-v4.19/drivers/gpu/drm/tegra/
Dhub.c89 return tegra_dc_readl(plane->dc, tegra_plane_offset(plane, offset)); in tegra_plane_readl()
179 value = tegra_dc_readl(dc, DC_CMD_STATE_CONTROL); in tegra_shared_plane_update()
199 value = tegra_dc_readl(dc, DC_CMD_STATE_CONTROL); in tegra_shared_plane_activate()
213 return tegra_dc_readl(dc, offset) & OWNER_MASK; in tegra_shared_plane_get_owner()
242 value = tegra_dc_readl(dc, offset); in tegra_shared_plane_set_owner()
665 value = tegra_dc_readl(dc, DC_CMD_IHUB_COMMON_MISC_CTL); in tegra_display_hub_update()
669 value = tegra_dc_readl(dc, DC_DISP_IHUB_COMMON_DISPLAY_FETCH_METER); in tegra_display_hub_update()
674 tegra_dc_readl(dc, DC_CMD_STATE_CONTROL); in tegra_display_hub_update()
676 tegra_dc_readl(dc, DC_CMD_STATE_CONTROL); in tegra_display_hub_update()
Ddc.c43 value = tegra_dc_readl(dc, offset); in tegra_dc_readl_active()
75 return tegra_dc_readl(plane->dc, tegra_plane_offset(plane, offset)); in tegra_plane_readl()
876 value = tegra_dc_readl(dc, DC_DISP_DISP_WIN_OPTIONS); in tegra_cursor_atomic_update()
880 value = tegra_dc_readl(dc, DC_DISP_BLEND_CURSOR_CONTROL); in tegra_cursor_atomic_update()
906 value = tegra_dc_readl(dc, DC_DISP_DISP_WIN_OPTIONS); in tegra_cursor_atomic_disable()
1436 offset, tegra_dc_readl(dc, offset)); in tegra_dc_show_regs()
1465 value = tegra_dc_readl(dc, DC_COM_CRC_CHECKSUM); in tegra_dc_show_crc()
1557 value = tegra_dc_readl(dc, DC_CMD_INT_MASK); in tegra_dc_enable_vblank()
1569 value = tegra_dc_readl(dc, DC_CMD_INT_MASK); in tegra_dc_disable_vblank()
1695 value = tegra_dc_readl(dc, DC_CMD_DISPLAY_COMMAND); in tegra_dc_stop()
[all …]
Drgb.c150 value = tegra_dc_readl(rgb->dc, DC_COM_PIN_OUTPUT_POLARITY(1)); in tegra_rgb_encoder_enable()
Dsor.c1533 value = tegra_dc_readl(dc, DC_DISP_DISP_WIN_OPTIONS); in tegra_sor_edp_disable()
1889 value = tegra_dc_readl(dc, DC_DISP_DISP_WIN_OPTIONS); in tegra_sor_edp_enable()
2177 value = tegra_dc_readl(dc, DC_DISP_DISP_WIN_OPTIONS); in tegra_sor_hdmi_disable()
2392 value = tegra_dc_readl(dc, DC_DISP_DISP_SIGNAL_OPTIONS0); in tegra_sor_hdmi_enable()
2487 value = tegra_dc_readl(dc, DC_DISP_DISP_COLOR_CONTROL); in tegra_sor_hdmi_enable()
2552 value = tegra_dc_readl(dc, DC_DISP_DISP_WIN_OPTIONS); in tegra_sor_hdmi_enable()
2562 value = tegra_dc_readl(dc, DC_DISP_CORE_SOR_SET_CONTROL(sor->index)); in tegra_sor_hdmi_enable()
Ddc.h118 static inline u32 tegra_dc_readl(struct tegra_dc *dc, unsigned int offset) in tegra_dc_readl() function
Ddsi.c865 value = tegra_dc_readl(dc, DC_DISP_DISP_WIN_OPTIONS); in tegra_dsi_encoder_disable()
932 value = tegra_dc_readl(dc, DC_DISP_DISP_WIN_OPTIONS); in tegra_dsi_encoder_enable()
Dhdmi.c1207 value = tegra_dc_readl(dc, DC_DISP_DISP_WIN_OPTIONS); in tegra_hdmi_encoder_disable()
1426 value = tegra_dc_readl(dc, DC_DISP_DISP_WIN_OPTIONS); in tegra_hdmi_encoder_enable()