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Searched refs:smc_state_table (Results 1 – 23 of 23) sorted by relevance

/Linux-v4.19/drivers/gpu/drm/amd/powerplay/smumgr/
Dtonga_smumgr.c520 smu_data->smc_state_table.LinkLevelCount = in tonga_populate_smc_link_level()
690 SMU72_Discrete_GraphicsLevel *levels = smu_data->smc_state_table.GraphicsLevel; in tonga_populate_all_graphic_levels()
703 &(smu_data->smc_state_table.GraphicsLevel[i])); in tonga_populate_all_graphic_levels()
709 smu_data->smc_state_table.GraphicsLevel[i].DeepSleepDivId = 0; in tonga_populate_all_graphic_levels()
713 smu_data->smc_state_table.GraphicsLevel[0].EnabledForActivity = 1; in tonga_populate_all_graphic_levels()
717 smu_data->smc_state_table.GraphicsLevel[dpm_table->sclk_table.count-1].DisplayWatermark = in tonga_populate_all_graphic_levels()
720 smu_data->smc_state_table.GraphicsDpmLevelCount = in tonga_populate_all_graphic_levels()
731 smu_data->smc_state_table.GraphicsLevel[i].pcieDpmLevel = in tonga_populate_all_graphic_levels()
761 smu_data->smc_state_table.GraphicsLevel[i].pcieDpmLevel = highest_pcie_level_enabled; in tonga_populate_all_graphic_levels()
764 smu_data->smc_state_table.GraphicsLevel[0].pcieDpmLevel = lowest_pcie_level_enabled; in tonga_populate_all_graphic_levels()
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Dfiji_smumgr.c502 SMU73_Discrete_DpmTable *dpm_table = &(smu_data->smc_state_table); in fiji_populate_bapm_parameters_in_dpm_table()
859 smu_data->smc_state_table.LinkLevelCount = in fiji_populate_smc_link_level()
1029 smu_data->smc_state_table.GraphicsLevel; in fiji_populate_all_graphic_levels()
1055 smu_data->smc_state_table.GraphicsDpmLevelCount = in fiji_populate_all_graphic_levels()
1244 smu_data->smc_state_table.MemoryLevel; in fiji_populate_all_memory_levels()
1269 smu_data->smc_state_table.MemoryDpmLevelCount = in fiji_populate_all_memory_levels()
1658 smu_data->smc_state_table.GraphicsBootLevel = level; in fiji_populate_smc_initailial_state()
1667 smu_data->smc_state_table.MemoryBootLevel = level; in fiji_populate_smc_initailial_state()
1712 smu_data->smc_state_table.ClockStretcherAmount = stretch_amount; in fiji_populate_clock_stretcher_data_table()
1716 smu_data->smc_state_table.Sclk_CKS_masterEn0_7 |= in fiji_populate_clock_stretcher_data_table()
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Dpolaris10_smumgr.c428 SMU74_Discrete_DpmTable *table = &(smu_data->smc_state_table); in polaris10_populate_bapm_parameters_in_dpm_table()
786 smu_data->smc_state_table.LinkLevelCount = in polaris10_populate_smc_link_level()
844 const SMU74_Discrete_DpmTable *table = &(smu_data->smc_state_table); in polaris10_calculate_sclk_params()
991 smu_data->smc_state_table.GraphicsLevel; in polaris10_populate_all_graphic_levels()
998 polaris10_get_sclk_range_table(hwmgr, &(smu_data->smc_state_table)); in polaris10_populate_all_graphic_levels()
1004 &(smu_data->smc_state_table.GraphicsLevel[i])); in polaris10_populate_all_graphic_levels()
1014 smu_data->smc_state_table.GraphicsLevel[0].SclkSetting.SSc_En = 0; in polaris10_populate_all_graphic_levels()
1016 smu_data->smc_state_table.GraphicsLevel[0].EnabledForActivity = 1; in polaris10_populate_all_graphic_levels()
1017 smu_data->smc_state_table.GraphicsDpmLevelCount = in polaris10_populate_all_graphic_levels()
1134 smu_data->smc_state_table.MemoryLevel; in polaris10_populate_all_memory_levels()
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Dci_smumgr.c480 smu_data->smc_state_table.GraphicsLevel; in ci_populate_all_graphic_levels()
490 smu_data->smc_state_table.GraphicsLevel[i].DeepSleepDivId = 0; in ci_populate_all_graphic_levels()
492 smu_data->smc_state_table.GraphicsLevel[i].DisplayWatermark = in ci_populate_all_graphic_levels()
496 smu_data->smc_state_table.GraphicsLevel[0].EnabledForActivity = 1; in ci_populate_all_graphic_levels()
498 smu_data->smc_state_table.GraphicsDpmLevelCount = (u8)dpm_table->sclk_table.count; in ci_populate_all_graphic_levels()
717 SMU7_Discrete_DpmTable *dpm_table = &(smu_data->smc_state_table); in ci_populate_bapm_parameters_in_dpm_table()
1012 smu_data->smc_state_table.LinkLevelCount = in ci_populate_smc_link_level()
1307 SMU7_Discrete_MemoryLevel *levels = smu_data->smc_state_table.MemoryLevel; in ci_populate_all_memory_levels()
1316 &(smu_data->smc_state_table.MemoryLevel[i])); in ci_populate_all_memory_levels()
1321 smu_data->smc_state_table.MemoryLevel[0].EnabledForActivity = 1; in ci_populate_all_memory_levels()
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Dvegam_smumgr.c339 smu_data->smc_state_table.UvdBootLevel = 0; in vegam_update_uvd_smc_table()
341 smu_data->smc_state_table.UvdBootLevel = in vegam_update_uvd_smc_table()
350 mm_boot_level_value |= smu_data->smc_state_table.UvdBootLevel << 24; in vegam_update_uvd_smc_table()
360 (uint32_t)(1 << smu_data->smc_state_table.UvdBootLevel)); in vegam_update_uvd_smc_table()
373 smu_data->smc_state_table.VceBootLevel = in vegam_update_vce_smc_table()
376 smu_data->smc_state_table.VceBootLevel = 0; in vegam_update_vce_smc_table()
385 mm_boot_level_value |= smu_data->smc_state_table.VceBootLevel << 16; in vegam_update_vce_smc_table()
392 (uint32_t)1 << smu_data->smc_state_table.VceBootLevel); in vegam_update_vce_smc_table()
590 smu_data->smc_state_table.LinkLevelCount = in vegam_populate_smc_link_level()
721 const SMU75_Discrete_DpmTable *table = &(smu_data->smc_state_table); in vegam_calculate_sclk_params()
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Diceland_smumgr.c787 smu_data->smc_state_table.LinkLevelCount = in iceland_populate_smc_link_level()
970 SMU71_Discrete_GraphicsLevel *levels = smu_data->smc_state_table.GraphicsLevel; in iceland_populate_all_graphic_levels()
983 &(smu_data->smc_state_table.GraphicsLevel[i])); in iceland_populate_all_graphic_levels()
989 smu_data->smc_state_table.GraphicsLevel[i].DeepSleepDivId = 0; in iceland_populate_all_graphic_levels()
993 smu_data->smc_state_table.GraphicsLevel[0].EnabledForActivity = 1; in iceland_populate_all_graphic_levels()
997 smu_data->smc_state_table.GraphicsLevel[dpm_table->sclk_table.count-1].DisplayWatermark = in iceland_populate_all_graphic_levels()
1000 smu_data->smc_state_table.GraphicsDpmLevelCount = in iceland_populate_all_graphic_levels()
1027 smu_data->smc_state_table.GraphicsLevel[i].pcieDpmLevel = highest_pcie_level_enabled; in iceland_populate_all_graphic_levels()
1031 smu_data->smc_state_table.GraphicsLevel[0].pcieDpmLevel = lowest_pcie_level_enabled; in iceland_populate_all_graphic_levels()
1034 smu_data->smc_state_table.GraphicsLevel[1].pcieDpmLevel = mid_pcie_level_enabled; in iceland_populate_all_graphic_levels()
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Dfiji_smumgr.h42 struct SMU73_Discrete_DpmTable smc_state_table; member
Dpolaris10_smumgr.h57 SMU74_Discrete_DpmTable smc_state_table; member
Diceland_smumgr.h62 struct SMU71_Discrete_DpmTable smc_state_table; member
Dvegam_smumgr.h66 SMU75_Discrete_DpmTable smc_state_table; member
Dci_smumgr.h68 struct SMU7_Discrete_DpmTable smc_state_table; member
Dtonga_smumgr.h66 struct SMU72_Discrete_DpmTable smc_state_table; member
/Linux-v4.19/drivers/gpu/drm/amd/powerplay/hwmgr/
Dvega10_hwmgr.c925 PPTable_t *pp_table = &(data->smc_state_table.pp_table); in vega10_setup_dpm_led_config()
1433 data->smc_state_table.pp_table.UlvOffsetVid = in vega10_populate_ulv_state()
1436 data->smc_state_table.pp_table.UlvSmnclkDid = in vega10_populate_ulv_state()
1438 data->smc_state_table.pp_table.UlvMp1clkDid = in vega10_populate_ulv_state()
1440 data->smc_state_table.pp_table.UlvGfxclkBypass = in vega10_populate_ulv_state()
1442 data->smc_state_table.pp_table.UlvPhaseSheddingPsi0 = in vega10_populate_ulv_state()
1444 data->smc_state_table.pp_table.UlvPhaseSheddingPsi1 = in vega10_populate_ulv_state()
1471 PPTable_t *pp_table = &(data->smc_state_table.pp_table); in vega10_populate_smc_link_levels()
1629 PPTable_t *pp_table = &(data->smc_state_table.pp_table); in vega10_populate_all_graphic_levels()
1684 PPTable_t *pp_table = &(data->smc_state_table.pp_table); in vega10_populate_vddc_soc_levels()
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Dvega12_thermal.c258 PPTable_t *table = &(data->smc_state_table.pp_table); in vega12_thermal_setup_fan_table()
Dvega10_thermal.c505 PPTable_t *table = &(data->smc_state_table.pp_table); in vega10_thermal_setup_fan_table()
549 (uint8_t *)(&(data->smc_state_table.pp_table)), in vega10_thermal_setup_fan_table()
Dvega10_hwmgr.h380 struct vega10_smc_state_table smc_state_table; member
Dvega12_hwmgr.h393 struct vega12_smc_state_table smc_state_table; member
Dvega12_hwmgr.c723 PPTable_t *pp_table = &(data->smc_state_table.pp_table); in vega12_init_smc_table()
1778 Watermarks_t *table = &(data->smc_state_table.water_marks_table); in vega12_set_watermarks_for_clocks_ranges()
2102 Watermarks_t *wm_table = &(data->smc_state_table.water_marks_table); in vega12_display_configuration_changed_task()
Dvega10_powertune.c1290 PPTable_t *table = &(data->smc_state_table.pp_table); in vega10_initialize_power_tune_defaults()
/Linux-v4.19/drivers/gpu/drm/radeon/
Dci_dpm.c433 SMU7_Discrete_DpmTable *dpm_table = &pi->smc_state_table; in ci_populate_bapm_parameters_in_dpm_table()
1303 SMU7_Discrete_DpmTable *table = &pi->smc_state_table; in ci_init_fps_limits()
2594 pi->smc_state_table.GraphicsBootLevel = level; in ci_populate_smc_initial_state()
2602 pi->smc_state_table.MemoryBootLevel = level; in ci_populate_smc_initial_state()
2641 pi->smc_state_table.LinkLevelCount = (u8)dpm_table->pcie_speed_table.count; in ci_populate_smc_link_level()
3282 SMU7_Discrete_GraphicsLevel *levels = pi->smc_state_table.GraphicsLevel; in ci_populate_all_graphic_levels()
3291 &pi->smc_state_table.GraphicsLevel[i]); in ci_populate_all_graphic_levels()
3295 pi->smc_state_table.GraphicsLevel[i].DeepSleepDivId = 0; in ci_populate_all_graphic_levels()
3297 pi->smc_state_table.GraphicsLevel[i].DisplayWatermark = in ci_populate_all_graphic_levels()
3300 pi->smc_state_table.GraphicsLevel[0].EnabledForActivity = 1; in ci_populate_all_graphic_levels()
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Dci_dpm.h223 SMU7_Discrete_DpmTable smc_state_table; member
/Linux-v4.19/drivers/gpu/drm/amd/amdgpu/
Dci_dpm.c558 SMU7_Discrete_DpmTable *dpm_table = &pi->smc_state_table; in ci_populate_bapm_parameters_in_dpm_table()
1457 SMU7_Discrete_DpmTable *table = &pi->smc_state_table; in ci_init_fps_limits()
2732 pi->smc_state_table.GraphicsBootLevel = level; in ci_populate_smc_initial_state()
2740 pi->smc_state_table.MemoryBootLevel = level; in ci_populate_smc_initial_state()
2779 pi->smc_state_table.LinkLevelCount = (u8)dpm_table->pcie_speed_table.count; in ci_populate_smc_link_level()
3427 SMU7_Discrete_GraphicsLevel *levels = pi->smc_state_table.GraphicsLevel; in ci_populate_all_graphic_levels()
3436 &pi->smc_state_table.GraphicsLevel[i]); in ci_populate_all_graphic_levels()
3440 pi->smc_state_table.GraphicsLevel[i].DeepSleepDivId = 0; in ci_populate_all_graphic_levels()
3442 pi->smc_state_table.GraphicsLevel[i].DisplayWatermark = in ci_populate_all_graphic_levels()
3445 pi->smc_state_table.GraphicsLevel[0].EnabledForActivity = 1; in ci_populate_all_graphic_levels()
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Dci_dpm.h225 SMU7_Discrete_DpmTable smc_state_table; member