433 	SMU7_Discrete_DpmTable  *dpm_table = &pi->smc_state_table;  in ci_populate_bapm_parameters_in_dpm_table()
1303 	SMU7_Discrete_DpmTable *table = &pi->smc_state_table;  in ci_init_fps_limits()
2594 			pi->smc_state_table.GraphicsBootLevel = level;  in ci_populate_smc_initial_state()
2602 			pi->smc_state_table.MemoryBootLevel = level;  in ci_populate_smc_initial_state()
2641 	pi->smc_state_table.LinkLevelCount = (u8)dpm_table->pcie_speed_table.count;  in ci_populate_smc_link_level()
3282 	SMU7_Discrete_GraphicsLevel *levels = pi->smc_state_table.GraphicsLevel;  in ci_populate_all_graphic_levels()
3291 						       &pi->smc_state_table.GraphicsLevel[i]);  in ci_populate_all_graphic_levels()
3295 			pi->smc_state_table.GraphicsLevel[i].DeepSleepDivId = 0;  in ci_populate_all_graphic_levels()
3297 			pi->smc_state_table.GraphicsLevel[i].DisplayWatermark =  in ci_populate_all_graphic_levels()
3300 	pi->smc_state_table.GraphicsLevel[0].EnabledForActivity = 1;  in ci_populate_all_graphic_levels()
3302 	pi->smc_state_table.GraphicsDpmLevelCount = (u8)dpm_table->sclk_table.count;  in ci_populate_all_graphic_levels()
3329 	SMU7_Discrete_MemoryLevel *levels = pi->smc_state_table.MemoryLevel;  in ci_populate_all_memory_levels()
3339 						      &pi->smc_state_table.MemoryLevel[i]);  in ci_populate_all_memory_levels()
3344 	pi->smc_state_table.MemoryLevel[0].EnabledForActivity = 1;  in ci_populate_all_memory_levels()
3348 		pi->smc_state_table.MemoryLevel[1].MinVddc =  in ci_populate_all_memory_levels()
3349 			pi->smc_state_table.MemoryLevel[0].MinVddc;  in ci_populate_all_memory_levels()
3350 		pi->smc_state_table.MemoryLevel[1].MinVddcPhases =  in ci_populate_all_memory_levels()
3351 			pi->smc_state_table.MemoryLevel[0].MinVddcPhases;  in ci_populate_all_memory_levels()
3354 	pi->smc_state_table.MemoryLevel[0].ActivityLevel = cpu_to_be16(0x1F);  in ci_populate_all_memory_levels()
3356 	pi->smc_state_table.MemoryDpmLevelCount = (u8)dpm_table->mclk_table.count;  in ci_populate_all_memory_levels()
3360 	pi->smc_state_table.MemoryLevel[dpm_table->mclk_table.count - 1].DisplayWatermark =  in ci_populate_all_memory_levels()
3558 	SMU7_Discrete_DpmTable *table = &pi->smc_state_table;  in ci_init_smc_table()
3580 		ret = ci_populate_ulv_state(rdev, &pi->smc_state_table.Ulv);  in ci_init_smc_table()
3629 				 (u32 *)&pi->smc_state_table.GraphicsBootLevel);  in ci_init_smc_table()
3633 				 (u32 *)&pi->smc_state_table.MemoryBootLevel);  in ci_init_smc_table()
4083 			pi->smc_state_table.UvdBootLevel = 0;  in ci_update_uvd_dpm()
4085 			pi->smc_state_table.UvdBootLevel =  in ci_update_uvd_dpm()
4090 		tmp |= UvdBootLevel(pi->smc_state_table.UvdBootLevel);  in ci_update_uvd_dpm()
4125 			pi->smc_state_table.VceBootLevel = ci_get_vce_boot_level(rdev);  in ci_update_vce_dpm()
4128 			tmp |= VceBootLevel(pi->smc_state_table.VceBootLevel);  in ci_update_vce_dpm()
4154 		pi->smc_state_table.AcpBootLevel = 0;
4158 		tmp |= AcpBootLevel(pi->smc_state_table.AcpBootLevel);
5822 	dpm_table = &pi->smc_state_table;  in ci_dpm_init()