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Searched refs:mux_reg (Results 1 – 25 of 30) sorted by relevance

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/Linux-v4.19/drivers/clk/samsung/
Dclk-cpu.c90 static void wait_until_mux_stable(void __iomem *mux_reg, u32 mux_pos, in wait_until_mux_stable() argument
96 if (((readl(mux_reg) >> mux_pos) & MUX_MASK) == mux_value) in wait_until_mux_stable()
100 if (((readl(mux_reg) >> mux_pos) & MUX_MASK) == mux_value) in wait_until_mux_stable()
157 unsigned long div0, div1 = 0, mux_reg; in exynos_cpuclk_pre_rate_change() local
209 mux_reg = readl(base + E4210_SRC_CPU); in exynos_cpuclk_pre_rate_change()
210 writel(mux_reg | (1 << 16), base + E4210_SRC_CPU); in exynos_cpuclk_pre_rate_change()
233 unsigned long mux_reg; in exynos_cpuclk_post_rate_change() local
248 mux_reg = readl(base + E4210_SRC_CPU); in exynos_cpuclk_post_rate_change()
249 writel(mux_reg & ~(1 << 16), base + E4210_SRC_CPU); in exynos_cpuclk_post_rate_change()
285 unsigned long div0, div1 = 0, mux_reg; in exynos5433_cpuclk_pre_rate_change() local
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/Linux-v4.19/arch/arm/mach-omap1/include/mach/
Dmux.h41 .mux_reg = FUNC_MUX_CTRL_##reg, \
55 .mux_reg = OMAP7XX_IO_CONF_##reg, \
66 #define MUX_REG(reg, mode_offset, mode) .mux_reg = FUNC_MUX_CTRL_##reg, \
78 .mux_reg = OMAP7XX_IO_CONF_##reg, \
88 #define MUX_CFG(desc, mux_reg, mode_offset, mode, \ argument
94 MUX_REG(mux_reg, mode_offset, mode) \
107 #define MUX_CFG_7XX(desc, mux_reg, mode_offset, mode, \ argument
112 MUX_REG_7XX(mux_reg, mode_offset, mode) \
113 PULL_REG_7XX(mux_reg, pull_bit, pull_status) \
119 const unsigned int mux_reg; member
/Linux-v4.19/drivers/pinctrl/freescale/
Dpinctrl-imx.c174 if (pin_reg->mux_reg == -1) { in imx_pmx_set()
182 reg = readl(ipctl->base + pin_reg->mux_reg); in imx_pmx_set()
185 writel(reg, ipctl->base + pin_reg->mux_reg); in imx_pmx_set()
187 pin_reg->mux_reg, reg); in imx_pmx_set()
189 writel(pin->mux_mode, ipctl->base + pin_reg->mux_reg); in imx_pmx_set()
191 pin_reg->mux_reg, pin->mux_mode); in imx_pmx_set()
490 u32 mux_reg = be32_to_cpu(*list++); in imx_pinctrl_parse_groups() local
496 if (!(info->flags & ZERO_OFFSET_VALID) && !mux_reg) in imx_pinctrl_parse_groups()
497 mux_reg = -1; in imx_pinctrl_parse_groups()
500 conf_reg = mux_reg; in imx_pinctrl_parse_groups()
[all …]
Dpinctrl-vf610.c302 if (pin_reg->mux_reg == -1) in vf610_pmx_gpio_set_direction()
306 reg = readl(ipctl->base + pin_reg->mux_reg); in vf610_pmx_gpio_set_direction()
311 writel(reg, ipctl->base + pin_reg->mux_reg); in vf610_pmx_gpio_set_direction()
Dpinctrl-imx7ulp.c309 if (pin_reg->mux_reg == -1) in imx7ulp_pmx_gpio_set_direction()
312 reg = readl(ipctl->base + pin_reg->mux_reg); in imx7ulp_pmx_gpio_set_direction()
317 writel(reg, ipctl->base + pin_reg->mux_reg); in imx7ulp_pmx_gpio_set_direction()
Dpinctrl-imx.h44 s16 mux_reg; member
/Linux-v4.19/arch/arm/mach-davinci/
Dmux.h23 .mux_reg = PINMUX(muxreg), \
34 .mux_reg = INTMUX, \
45 .mux_reg = EVTMUX, \
Dmux.c70 reg_orig = __raw_readl(pinmux_base + cfg->mux_reg); in davinci_cfg_reg()
82 __raw_writel(reg, pinmux_base + cfg->mux_reg); in davinci_cfg_reg()
96 cfg->mux_reg_name, cfg->mux_reg, reg_orig, reg); in davinci_cfg_reg()
/Linux-v4.19/drivers/pinctrl/tegra/
Dpinctrl-tegra.c266 if (WARN_ON(g->mux_reg < 0)) in tegra_pinctrl_set_mux()
276 val = pmx_readl(pmx, g->mux_bank, g->mux_reg); in tegra_pinctrl_set_mux()
279 pmx_writel(pmx, val, g->mux_bank, g->mux_reg); in tegra_pinctrl_set_mux()
312 *reg = g->mux_reg; in tegra_pinconf_reg()
318 *reg = g->mux_reg; in tegra_pinconf_reg()
324 *reg = g->mux_reg; in tegra_pinconf_reg()
330 *reg = g->mux_reg; in tegra_pinconf_reg()
336 *reg = g->mux_reg; in tegra_pinconf_reg()
343 *reg = g->mux_reg; in tegra_pinconf_reg()
354 *reg = g->mux_reg; in tegra_pinconf_reg()
[all …]
Dpinctrl-tegra.h146 s16 mux_reg; member
Dpinctrl-tegra20.c1991 .mux_reg = ((mux_r) - PIN_MUX_CTL_REG_A), \
2015 .mux_reg = -1, \
2031 .mux_reg = -1, \
/Linux-v4.19/drivers/clk/mediatek/
Dclk-mtk.h73 uint32_t mux_reg; member
95 .mux_reg = _reg, \
117 .mux_reg = _reg, \
Dclk-cpumux.c74 cpumux->reg = mux->mux_reg; in mtk_clk_register_cpumux()
Dclk-mtk.c166 mux->reg = base + mc->mux_reg; in mtk_clk_register_composite()
/Linux-v4.19/arch/arm/mach-omap1/
Dmux.c355 if (cfg->mux_reg) { in omap1_cfg_reg()
359 reg_orig = omap_readl(cfg->mux_reg); in omap1_cfg_reg()
372 omap_writel(reg, cfg->mux_reg); in omap1_cfg_reg()
431 cfg->mux_reg_name, cfg->mux_reg, reg_orig, reg); in omap1_cfg_reg()
/Linux-v4.19/drivers/clk/microchip/
Dclk-core.c768 void __iomem *mux_reg; member
829 v = (readl(sclk->mux_reg) >> OSC_CUR_SHIFT) & OSC_CUR_MASK; in sclk_get_parent()
853 v = readl(sclk->mux_reg); in sclk_set_parent()
859 writel(v, sclk->mux_reg); in sclk_set_parent()
862 writel(OSC_SWEN, PIC32_SET(sclk->mux_reg)); in sclk_set_parent()
880 cosc = (readl(sclk->mux_reg) >> OSC_CUR_SHIFT) & OSC_CUR_MASK; in sclk_set_parent()
942 sclk->mux_reg = data->mux_reg + core->iobase; in pic32_sys_clk_register()
Dclk-core.h37 const u32 mux_reg; member
/Linux-v4.19/drivers/pinctrl/
Dpinctrl-pistachio.c92 int mux_reg; member
647 .mux_reg = -1, \
661 .mux_reg = -1, \
675 .mux_reg = _reg, \
957 if (pg->mux_reg > 0) { in pistachio_pinmux_enable()
968 val = pctl_readl(pctl, pg->mux_reg); in pistachio_pinmux_enable()
971 pctl_writel(pctl, val, pg->mux_reg); in pistachio_pinmux_enable()
/Linux-v4.19/Documentation/devicetree/bindings/pinctrl/
Dfsl,imx6sx-pinctrl.txt9 setting for one pin. The first 5 integers <mux_reg conf_reg input_reg mux_val
Dfsl,imx6sll-pinctrl.txt9 setting for one pin. The first 5 integers <mux_reg conf_reg input_reg mux_val
Dfsl,imx6ul-pinctrl.txt10 setting for one pin. The first 5 integers <mux_reg conf_reg input_reg mux_val
Dfsl,imx8mq-pinctrl.txt13 setting for one pin. The first 5 integers <mux_reg conf_reg input_reg mux_val
Dfsl,imx7d-pinctrl.txt32 setting for one pin. The first 5 integers <mux_reg conf_reg input_reg mux_val
Dfsl,imx-pinctrl.txt26 setting for one pin. The first 5 integers <mux_reg conf_reg input_reg mux_val
/Linux-v4.19/arch/arm/mach-davinci/include/mach/
Dmux.h25 const unsigned char mux_reg; member

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