90 static void wait_until_mux_stable(void __iomem *mux_reg, u32 mux_pos,  in wait_until_mux_stable()  argument
96 		if (((readl(mux_reg) >> mux_pos) & MUX_MASK) == mux_value)  in wait_until_mux_stable()
100 	if (((readl(mux_reg) >> mux_pos) & MUX_MASK) == mux_value)  in wait_until_mux_stable()
157 	unsigned long div0, div1 = 0, mux_reg;  in exynos_cpuclk_pre_rate_change()  local
209 	mux_reg = readl(base + E4210_SRC_CPU);  in exynos_cpuclk_pre_rate_change()
210 	writel(mux_reg | (1 << 16), base + E4210_SRC_CPU);  in exynos_cpuclk_pre_rate_change()
233 	unsigned long mux_reg;  in exynos_cpuclk_post_rate_change()  local
248 	mux_reg = readl(base + E4210_SRC_CPU);  in exynos_cpuclk_post_rate_change()
249 	writel(mux_reg & ~(1 << 16), base + E4210_SRC_CPU);  in exynos_cpuclk_post_rate_change()
285 	unsigned long div0, div1 = 0, mux_reg;  in exynos5433_cpuclk_pre_rate_change()  local
323 	mux_reg = readl(base + E5433_MUX_SEL2);  in exynos5433_cpuclk_pre_rate_change()
324 	writel(mux_reg | 1, base + E5433_MUX_SEL2);  in exynos5433_cpuclk_pre_rate_change()
343 	unsigned long mux_reg;  in exynos5433_cpuclk_post_rate_change()  local
349 	mux_reg = readl(base + E5433_MUX_SEL2);  in exynos5433_cpuclk_post_rate_change()
350 	writel(mux_reg & ~1, base + E5433_MUX_SEL2);  in exynos5433_cpuclk_post_rate_change()