Home
last modified time | relevance | path

Searched refs:ctrl_reg (Results 1 – 25 of 71) sorted by relevance

123

/Linux-v4.19/drivers/rtc/
Drtc-pm8xxx.c88 unsigned int ctrl_reg, rtc_ctrl_reg; in pm8xxx_rtc_set_time() local
106 rc = regmap_read(rtc_dd->regmap, regs->alarm_ctrl, &ctrl_reg); in pm8xxx_rtc_set_time()
110 if (ctrl_reg & regs->alarm_en) { in pm8xxx_rtc_set_time()
112 ctrl_reg &= ~regs->alarm_en; in pm8xxx_rtc_set_time()
113 rc = regmap_write(rtc_dd->regmap, regs->alarm_ctrl, ctrl_reg); in pm8xxx_rtc_set_time()
168 ctrl_reg |= regs->alarm_en; in pm8xxx_rtc_set_time()
169 rc = regmap_write(rtc_dd->regmap, regs->alarm_ctrl, ctrl_reg); in pm8xxx_rtc_set_time()
231 unsigned int ctrl_reg; in pm8xxx_rtc_set_alarm() local
252 rc = regmap_read(rtc_dd->regmap, regs->alarm_ctrl, &ctrl_reg); in pm8xxx_rtc_set_alarm()
257 ctrl_reg |= regs->alarm_en; in pm8xxx_rtc_set_alarm()
[all …]
/Linux-v4.19/drivers/regulator/
Dvctrl-regulator.c45 struct regulator *ctrl_reg; member
90 int ctrl_uV = regulator_get_voltage(vctrl->ctrl_reg); in vctrl_get_voltage()
100 struct regulator *ctrl_reg = vctrl->ctrl_reg; in vctrl_set_voltage() local
101 int orig_ctrl_uV = regulator_get_voltage(ctrl_reg); in vctrl_set_voltage()
108 ctrl_reg, in vctrl_set_voltage()
125 ret = regulator_set_voltage(ctrl_reg, in vctrl_set_voltage()
141 regulator_set_voltage(ctrl_reg, orig_ctrl_uV, orig_ctrl_uV); in vctrl_set_voltage()
157 struct regulator *ctrl_reg = vctrl->ctrl_reg; in vctrl_set_voltage_sel() local
166 ret = regulator_set_voltage(ctrl_reg, in vctrl_set_voltage_sel()
184 ret = regulator_set_voltage(ctrl_reg, in vctrl_set_voltage_sel()
[all …]
/Linux-v4.19/drivers/watchdog/
Dmachzwd.c192 unsigned int ctrl_reg = 0; in zf_timer_off() local
200 ctrl_reg = zf_get_control(); in zf_timer_off()
201 ctrl_reg |= (ENABLE_WD1|ENABLE_WD2); /* disable wd1 and wd2 */ in zf_timer_off()
202 ctrl_reg &= ~(ENABLE_WD1|ENABLE_WD2); in zf_timer_off()
203 zf_set_control(ctrl_reg); in zf_timer_off()
215 unsigned int ctrl_reg = 0; in zf_timer_on() local
231 ctrl_reg = zf_get_control(); in zf_timer_on()
232 ctrl_reg |= (ENABLE_WD1|zf_action); in zf_timer_on()
233 zf_set_control(ctrl_reg); in zf_timer_on()
242 unsigned int ctrl_reg = 0; in zf_ping() local
[all …]
/Linux-v4.19/drivers/clk/microchip/
Dclk-core.c98 void __iomem *ctrl_reg; member
108 return readl(pb->ctrl_reg) & PB_DIV_ENABLE; in pbclk_is_enabled()
115 writel(PB_DIV_ENABLE, PIC32_SET(pb->ctrl_reg)); in pbclk_enable()
123 writel(PB_DIV_ENABLE, PIC32_CLR(pb->ctrl_reg)); in pbclk_disable()
154 return ((readl(pb->ctrl_reg) >> PB_DIV_SHIFT) & PB_DIV_MASK) + 1; in pbclk_read_pbdiv()
181 err = readl_poll_timeout(pb->ctrl_reg, v, v & PB_DIV_READY, in pbclk_set_rate()
192 v = readl(pb->ctrl_reg); in pbclk_set_rate()
198 writel(v, pb->ctrl_reg); in pbclk_set_rate()
203 err = readl_poll_timeout(pb->ctrl_reg, v, v & PB_DIV_READY, in pbclk_set_rate()
233 pbclk->ctrl_reg = desc->ctrl_reg + core->iobase; in pic32_periph_clk_register()
[all …]
Dclk-core.h29 const u32 ctrl_reg; member
46 const u32 ctrl_reg; member
53 const u32 ctrl_reg; member
/Linux-v4.19/drivers/bluetooth/
Dbluecard_cs.c79 unsigned char ctrl_reg; member
265 info->ctrl_reg |= REG_CONTROL_RTS; in bluecard_write_wakeup()
266 outb(info->ctrl_reg, iobase + REG_CONTROL); in bluecard_write_wakeup()
308 info->ctrl_reg &= ~0x03; in bluecard_write_wakeup()
309 info->ctrl_reg |= baud_reg; in bluecard_write_wakeup()
310 outb(info->ctrl_reg, iobase + REG_CONTROL); in bluecard_write_wakeup()
313 info->ctrl_reg &= ~REG_CONTROL_RTS; in bluecard_write_wakeup()
314 outb(info->ctrl_reg, iobase + REG_CONTROL); in bluecard_write_wakeup()
513 info->ctrl_reg &= ~REG_CONTROL_INTERRUPT; in bluecard_interrupt()
514 outb(info->ctrl_reg, iobase + REG_CONTROL); in bluecard_interrupt()
[all …]
/Linux-v4.19/drivers/pci/hotplug/
Dshpchp.h175 struct ctrl_reg { struct
193 BASE_OFFSET = offsetof(struct ctrl_reg, base_offset), argument
194 SLOT_AVAIL1 = offsetof(struct ctrl_reg, slot_avail1),
195 SLOT_AVAIL2 = offsetof(struct ctrl_reg, slot_avail2),
196 SLOT_CONFIG = offsetof(struct ctrl_reg, slot_config),
197 SEC_BUS_CONFIG = offsetof(struct ctrl_reg, sec_bus_config),
198 MSI_CTRL = offsetof(struct ctrl_reg, msi_ctrl),
199 PROG_INTERFACE = offsetof(struct ctrl_reg, prog_interface),
200 CMD = offsetof(struct ctrl_reg, cmd),
201 CMD_STATUS = offsetof(struct ctrl_reg, cmd_status),
[all …]
Dcpqphp.h108 struct ctrl_reg { /* offset */ struct
140 SLOT_RST = offsetof(struct ctrl_reg, slot_RST), argument
141 SLOT_ENABLE = offsetof(struct ctrl_reg, slot_enable),
142 MISC = offsetof(struct ctrl_reg, misc),
143 LED_CONTROL = offsetof(struct ctrl_reg, led_control),
144 INT_INPUT_CLEAR = offsetof(struct ctrl_reg, int_input_clear),
145 INT_MASK = offsetof(struct ctrl_reg, int_mask),
146 CTRL_RESERVED0 = offsetof(struct ctrl_reg, reserved0),
147 CTRL_RESERVED1 = offsetof(struct ctrl_reg, reserved1),
148 CTRL_RESERVED2 = offsetof(struct ctrl_reg, reserved1),
[all …]
/Linux-v4.19/drivers/net/wireless/st/cw1200/
Dbh.c181 u16 *ctrl_reg) in cw1200_bh_read_ctrl_reg() argument
186 ST90TDS_CONTROL_REG_ID, ctrl_reg); in cw1200_bh_read_ctrl_reg()
189 ST90TDS_CONTROL_REG_ID, ctrl_reg); in cw1200_bh_read_ctrl_reg()
199 u16 ctrl_reg; in cw1200_device_wakeup() local
216 ret = cw1200_bh_read_ctrl_reg(priv, &ctrl_reg); in cw1200_device_wakeup()
223 if (ctrl_reg & ST90TDS_CONT_RDY_BIT) { in cw1200_device_wakeup()
241 uint16_t *ctrl_reg, in cw1200_bh_rx_helper() argument
255 read_len = (*ctrl_reg & ST90TDS_CONT_NEXT_LEN_MASK) * 2; in cw1200_bh_rx_helper()
262 read_len, *ctrl_reg); in cw1200_bh_rx_helper()
296 *ctrl_reg = __le16_to_cpu( in cw1200_bh_rx_helper()
[all …]
/Linux-v4.19/drivers/clk/hisilicon/
Dclk-hix5hd2.c139 u32 ctrl_reg; member
151 void __iomem *ctrl_reg; member
177 val = readl_relaxed(clk->ctrl_reg); in clk_ether_prepare()
179 writel_relaxed(val, clk->ctrl_reg); in clk_ether_prepare()
181 writel_relaxed(val, clk->ctrl_reg); in clk_ether_prepare()
206 val = readl_relaxed(clk->ctrl_reg); in clk_ether_unprepare()
208 writel_relaxed(val, clk->ctrl_reg); in clk_ether_unprepare()
221 val = readl_relaxed(clk->ctrl_reg); in clk_complex_enable()
224 writel_relaxed(val, clk->ctrl_reg); in clk_complex_enable()
239 val = readl_relaxed(clk->ctrl_reg); in clk_complex_disable()
[all …]
/Linux-v4.19/drivers/spi/
Dspi-jcore.c43 static int jcore_spi_wait(void __iomem *ctrl_reg) in jcore_spi_wait() argument
48 if (!(readl(ctrl_reg) & JCORE_SPI_STAT_BUSY)) in jcore_spi_wait()
58 void __iomem *ctrl_reg = hw->base + CTRL_REG; in jcore_spi_program() local
60 if (jcore_spi_wait(ctrl_reg)) in jcore_spi_program()
64 writel(hw->cs_reg | hw->speed_reg, ctrl_reg); in jcore_spi_program()
100 void __iomem *ctrl_reg = hw->base + CTRL_REG; in jcore_spi_txrx() local
118 if (jcore_spi_wait(ctrl_reg)) in jcore_spi_txrx()
122 writel(xmit, ctrl_reg); in jcore_spi_txrx()
124 if (jcore_spi_wait(ctrl_reg)) in jcore_spi_txrx()
Dspi-cadence.c159 u32 ctrl_reg = CDNS_SPI_CR_DEFAULT; in cdns_spi_init_hw() local
162 ctrl_reg |= CDNS_SPI_CR_PERI_SEL; in cdns_spi_init_hw()
172 cdns_spi_write(xspi, CDNS_SPI_CR, ctrl_reg); in cdns_spi_init_hw()
184 u32 ctrl_reg; in cdns_spi_chipselect() local
186 ctrl_reg = cdns_spi_read(xspi, CDNS_SPI_CR); in cdns_spi_chipselect()
190 ctrl_reg |= CDNS_SPI_CR_SSCTRL; in cdns_spi_chipselect()
193 ctrl_reg &= ~CDNS_SPI_CR_SSCTRL; in cdns_spi_chipselect()
195 ctrl_reg |= ((~(CDNS_SPI_SS0 << spi->chip_select)) << in cdns_spi_chipselect()
199 ctrl_reg |= (spi->chip_select << CDNS_SPI_SS_SHIFT) & in cdns_spi_chipselect()
203 cdns_spi_write(xspi, CDNS_SPI_CR, ctrl_reg); in cdns_spi_chipselect()
[all …]
/Linux-v4.19/drivers/misc/ibmasm/
Dlowlevel.h67 void __iomem *ctrl_reg = base_address + INTR_CONTROL_REGISTER; in ibmasm_enable_interrupts() local
68 writel( readl(ctrl_reg) & ~mask, ctrl_reg); in ibmasm_enable_interrupts()
73 void __iomem *ctrl_reg = base_address + INTR_CONTROL_REGISTER; in ibmasm_disable_interrupts() local
74 writel( readl(ctrl_reg) | mask, ctrl_reg); in ibmasm_disable_interrupts()
/Linux-v4.19/drivers/phy/marvell/
Dphy-berlin-sata.c65 static inline void phy_berlin_sata_reg_setbits(void __iomem *ctrl_reg, in phy_berlin_sata_reg_setbits() argument
71 writel(phy_base + reg, ctrl_reg + PORT_VSR_ADDR); in phy_berlin_sata_reg_setbits()
74 regval = readl(ctrl_reg + PORT_VSR_DATA); in phy_berlin_sata_reg_setbits()
77 writel(regval, ctrl_reg + PORT_VSR_DATA); in phy_berlin_sata_reg_setbits()
84 void __iomem *ctrl_reg = priv->base + 0x60 + (desc->index * 0x80); in phy_berlin_sata_power_on() local
104 phy_berlin_sata_reg_setbits(ctrl_reg, priv->phy_base, 0x01, in phy_berlin_sata_power_on()
108 phy_berlin_sata_reg_setbits(ctrl_reg, priv->phy_base, 0x25, in phy_berlin_sata_power_on()
112 phy_berlin_sata_reg_setbits(ctrl_reg, priv->phy_base, 0x23, in phy_berlin_sata_power_on()
116 phy_berlin_sata_reg_setbits(ctrl_reg, priv->phy_base, 0x02, in phy_berlin_sata_power_on()
120 regval = readl(ctrl_reg + PORT_SCR_CTL); in phy_berlin_sata_power_on()
[all …]
/Linux-v4.19/drivers/clocksource/
Dcadence_ttc_timer.c118 u32 ctrl_reg; in ttc_set_interval() local
121 ctrl_reg = readl_relaxed(timer->base_addr + TTC_CNT_CNTRL_OFFSET); in ttc_set_interval()
122 ctrl_reg |= TTC_CNT_CNTRL_DISABLE_MASK; in ttc_set_interval()
123 writel_relaxed(ctrl_reg, timer->base_addr + TTC_CNT_CNTRL_OFFSET); in ttc_set_interval()
131 ctrl_reg |= CNT_CNTRL_RESET; in ttc_set_interval()
132 ctrl_reg &= ~TTC_CNT_CNTRL_DISABLE_MASK; in ttc_set_interval()
133 writel_relaxed(ctrl_reg, timer->base_addr + TTC_CNT_CNTRL_OFFSET); in ttc_set_interval()
202 u32 ctrl_reg; in ttc_shutdown() local
204 ctrl_reg = readl_relaxed(timer->base_addr + TTC_CNT_CNTRL_OFFSET); in ttc_shutdown()
205 ctrl_reg |= TTC_CNT_CNTRL_DISABLE_MASK; in ttc_shutdown()
[all …]
/Linux-v4.19/drivers/input/rmi4/
Drmi_f30.c278 u8 *ctrl_reg = f30->ctrl_regs; in rmi_f30_initialize() local
303 f30->register_count, &ctrl_reg); in rmi_f30_initialize()
306 sizeof(u8), &ctrl_reg); in rmi_f30_initialize()
310 f30->register_count, &ctrl_reg); in rmi_f30_initialize()
313 f30->register_count, &ctrl_reg); in rmi_f30_initialize()
318 f30->register_count, &ctrl_reg); in rmi_f30_initialize()
322 &ctrl_reg); in rmi_f30_initialize()
328 f30->gpioled_count, &ctrl_reg); in rmi_f30_initialize()
334 f30->gpioled_count, &ctrl_reg); in rmi_f30_initialize()
339 f30->register_count, &ctrl_reg); in rmi_f30_initialize()
[all …]
/Linux-v4.19/drivers/net/ethernet/intel/ixgb/
Dixgb_hw.c49 u32 ctrl_reg; in ixgb_mac_reset() local
51 ctrl_reg = IXGB_CTRL0_RST | in ixgb_mac_reset()
62 IXGB_WRITE_REG_IO(hw, CTRL0, ctrl_reg); in ixgb_mac_reset()
64 IXGB_WRITE_REG(hw, CTRL0, ctrl_reg); in ixgb_mac_reset()
69 ctrl_reg = IXGB_READ_REG(hw, CTRL0); in ixgb_mac_reset()
72 ASSERT(!(ctrl_reg & IXGB_CTRL0_RST)); in ixgb_mac_reset()
76 ctrl_reg = /* Enable interrupt from XFP and SerDes */ in ixgb_mac_reset()
82 IXGB_WRITE_REG(hw, CTRL1, ctrl_reg); in ixgb_mac_reset()
89 return ctrl_reg; in ixgb_mac_reset()
100 u32 ctrl_reg; in ixgb_adapter_stop() local
[all …]
/Linux-v4.19/drivers/fpga/
Dsocfpga.c337 u32 ctrl_reg; in socfpga_fpga_cfg_mode_set() local
346 ctrl_reg = socfpga_fpga_readl(priv, SOCFPGA_FPGMGR_CTL_OFST); in socfpga_fpga_cfg_mode_set()
347 ctrl_reg &= ~SOCFPGA_FPGMGR_CTL_CDRATIO_MASK; in socfpga_fpga_cfg_mode_set()
348 ctrl_reg &= ~SOCFPGA_FPGMGR_CTL_CFGWDTH_MASK; in socfpga_fpga_cfg_mode_set()
349 ctrl_reg |= cfgmgr_modes[mode].ctrl; in socfpga_fpga_cfg_mode_set()
352 ctrl_reg &= ~SOCFPGA_FPGMGR_CTL_NCE; in socfpga_fpga_cfg_mode_set()
353 socfpga_fpga_writel(priv, SOCFPGA_FPGMGR_CTL_OFST, ctrl_reg); in socfpga_fpga_cfg_mode_set()
361 u32 ctrl_reg, status; in socfpga_fpga_reset() local
378 ctrl_reg = socfpga_fpga_readl(priv, SOCFPGA_FPGMGR_CTL_OFST); in socfpga_fpga_reset()
379 ctrl_reg |= SOCFPGA_FPGMGR_CTL_NCFGPULL; in socfpga_fpga_reset()
[all …]
/Linux-v4.19/drivers/tty/serial/
Dxilinx_uartps.c478 u32 ctrl_reg; in cdns_uart_clk_notifier_cb() local
508 ctrl_reg = readl(port->membase + CDNS_UART_CR); in cdns_uart_clk_notifier_cb()
509 ctrl_reg |= CDNS_UART_CR_TX_DIS | CDNS_UART_CR_RX_DIS; in cdns_uart_clk_notifier_cb()
510 writel(ctrl_reg, port->membase + CDNS_UART_CR); in cdns_uart_clk_notifier_cb()
535 ctrl_reg = readl(port->membase + CDNS_UART_CR); in cdns_uart_clk_notifier_cb()
536 ctrl_reg |= CDNS_UART_CR_TXRST | CDNS_UART_CR_RXRST; in cdns_uart_clk_notifier_cb()
537 writel(ctrl_reg, port->membase + CDNS_UART_CR); in cdns_uart_clk_notifier_cb()
549 ctrl_reg = readl(port->membase + CDNS_UART_CR); in cdns_uart_clk_notifier_cb()
550 ctrl_reg &= ~(CDNS_UART_CR_TX_DIS | CDNS_UART_CR_RX_DIS); in cdns_uart_clk_notifier_cb()
551 ctrl_reg |= CDNS_UART_CR_TX_EN | CDNS_UART_CR_RX_EN; in cdns_uart_clk_notifier_cb()
[all …]
/Linux-v4.19/drivers/isdn/hisax/
Dnj_s.c103 cs->hw.njet.ctrl_reg = 0xff; /* Reset On */ in reset_netjet_s()
104 byteout(cs->hw.njet.base + NETJET_CTRL, cs->hw.njet.ctrl_reg); in reset_netjet_s()
109 cs->hw.njet.ctrl_reg = 0x40; /* Reset Off and status read clear */ in reset_netjet_s()
111 cs->hw.njet.ctrl_reg = 0x00; /* Reset Off and status read clear */ in reset_netjet_s()
112 byteout(cs->hw.njet.base + NETJET_CTRL, cs->hw.njet.ctrl_reg); in reset_netjet_s()
195 cs->hw.njet.ctrl_reg = 0xff; /* Reset On */ in njs_cs_init()
196 byteout(cs->hw.njet.base + NETJET_CTRL, cs->hw.njet.ctrl_reg); in njs_cs_init()
199 cs->hw.njet.ctrl_reg = 0x00; /* Reset Off and status read clear */ in njs_cs_init()
200 byteout(cs->hw.njet.base + NETJET_CTRL, cs->hw.njet.ctrl_reg); in njs_cs_init()
Dnj_u.c86 cs->hw.njet.ctrl_reg = 0xff; /* Reset On */ in reset_netjet_u()
87 byteout(cs->hw.njet.base + NETJET_CTRL, cs->hw.njet.ctrl_reg); in reset_netjet_u()
89 cs->hw.njet.ctrl_reg = 0x40; /* Reset Off and status read clear */ in reset_netjet_u()
91 byteout(cs->hw.njet.base + NETJET_CTRL, cs->hw.njet.ctrl_reg); in reset_netjet_u()
156 cs->hw.njet.ctrl_reg = 0xff; /* Reset On */ in nju_cs_init()
157 byteout(cs->hw.njet.base + NETJET_CTRL, cs->hw.njet.ctrl_reg); in nju_cs_init()
160 cs->hw.njet.ctrl_reg = 0x00; /* Reset Off and status read clear */ in nju_cs_init()
161 byteout(cs->hw.njet.base + NETJET_CTRL, cs->hw.njet.ctrl_reg); in nju_cs_init()
Denternow_pci.c156 cs->hw.njet.ctrl_reg = 0x07; in reset_enpci()
157 outb(cs->hw.njet.ctrl_reg, cs->hw.njet.base + NETJET_CTRL); in reset_enpci()
160 cs->hw.njet.ctrl_reg = 0x30; in reset_enpci()
161 outb(cs->hw.njet.ctrl_reg, cs->hw.njet.base + NETJET_CTRL); in reset_enpci()
334 cs->hw.njet.ctrl_reg = 0x07; // geändert von 0xff in en_cs_init()
335 outb(cs->hw.njet.ctrl_reg, cs->hw.njet.base + NETJET_CTRL); in en_cs_init()
339 cs->hw.njet.ctrl_reg = 0x30; /* Reset Off and status read clear */ in en_cs_init()
340 outb(cs->hw.njet.ctrl_reg, cs->hw.njet.base + NETJET_CTRL); in en_cs_init()
/Linux-v4.19/drivers/i2c/busses/
Di2c-cadence.c366 unsigned int ctrl_reg; in cdns_i2c_mrecv() local
373 ctrl_reg = cdns_i2c_readreg(CDNS_I2C_CR_OFFSET); in cdns_i2c_mrecv()
374 ctrl_reg |= CDNS_I2C_CR_RW | CDNS_I2C_CR_CLR_FIFO; in cdns_i2c_mrecv()
386 ctrl_reg |= CDNS_I2C_CR_HOLD; in cdns_i2c_mrecv()
388 cdns_i2c_writereg(ctrl_reg, CDNS_I2C_CR_OFFSET); in cdns_i2c_mrecv()
427 unsigned int ctrl_reg; in cdns_i2c_msend() local
435 ctrl_reg = cdns_i2c_readreg(CDNS_I2C_CR_OFFSET); in cdns_i2c_msend()
436 ctrl_reg &= ~CDNS_I2C_CR_RW; in cdns_i2c_msend()
437 ctrl_reg |= CDNS_I2C_CR_CLR_FIFO; in cdns_i2c_msend()
444 ctrl_reg |= CDNS_I2C_CR_HOLD; in cdns_i2c_msend()
[all …]
/Linux-v4.19/drivers/media/platform/davinci/
Dvpif.h399 u32 ctrl_reg; in disable_raw_feature() local
401 ctrl_reg = VPIF_CH0_CTRL; in disable_raw_feature()
403 ctrl_reg = VPIF_CH1_CTRL; in disable_raw_feature()
406 vpif_clr_bit(ctrl_reg, VPIF_CH_VANC_EN_BIT); in disable_raw_feature()
408 vpif_clr_bit(ctrl_reg, VPIF_CH_HANC_EN_BIT); in disable_raw_feature()
413 u32 ctrl_reg; in enable_raw_feature() local
415 ctrl_reg = VPIF_CH0_CTRL; in enable_raw_feature()
417 ctrl_reg = VPIF_CH1_CTRL; in enable_raw_feature()
420 vpif_set_bit(ctrl_reg, VPIF_CH_VANC_EN_BIT); in enable_raw_feature()
422 vpif_set_bit(ctrl_reg, VPIF_CH_HANC_EN_BIT); in enable_raw_feature()
/Linux-v4.19/drivers/hwmon/
Daspeed-pwm-tacho.c210 u32 ctrl_reg; member
221 .ctrl_reg = ASPEED_PTCR_TYPEM_CTRL,
230 .ctrl_reg = ASPEED_PTCR_TYPEN_CTRL,
239 .ctrl_reg = ASPEED_PTCR_TYPEO_CTRL,
248 u32 ctrl_reg; member
261 .ctrl_reg = ASPEED_PTCR_CTRL,
272 .ctrl_reg = ASPEED_PTCR_CTRL,
283 .ctrl_reg = ASPEED_PTCR_CTRL,
294 .ctrl_reg = ASPEED_PTCR_CTRL,
305 .ctrl_reg = ASPEED_PTCR_CTRL_EXT,
[all …]

123