98 	void __iomem *ctrl_reg;  member
108 	return readl(pb->ctrl_reg) & PB_DIV_ENABLE;  in pbclk_is_enabled()
115 	writel(PB_DIV_ENABLE, PIC32_SET(pb->ctrl_reg));  in pbclk_enable()
123 	writel(PB_DIV_ENABLE, PIC32_CLR(pb->ctrl_reg));  in pbclk_disable()
154 	return ((readl(pb->ctrl_reg) >> PB_DIV_SHIFT) & PB_DIV_MASK) + 1;  in pbclk_read_pbdiv()
181 	err = readl_poll_timeout(pb->ctrl_reg, v, v & PB_DIV_READY,  in pbclk_set_rate()
192 	v = readl(pb->ctrl_reg);  in pbclk_set_rate()
198 	writel(v, pb->ctrl_reg);  in pbclk_set_rate()
203 	err = readl_poll_timeout(pb->ctrl_reg, v, v & PB_DIV_READY,  in pbclk_set_rate()
233 	pbclk->ctrl_reg = desc->ctrl_reg + core->iobase;  in pic32_periph_clk_register()
247 	void __iomem *ctrl_reg;  member
258 	return readl(refo->ctrl_reg) & REFO_ON;  in roclk_is_enabled()
265 	writel(REFO_ON | REFO_OE, PIC32_SET(refo->ctrl_reg));  in roclk_enable()
273 	writel(REFO_ON | REFO_OE, PIC32_CLR(refo->ctrl_reg));  in roclk_disable()
287 	v = (readl(refo->ctrl_reg) >> REFO_SEL_SHIFT) & REFO_SEL_MASK;  in roclk_get_parent()
370 	v = readl(refo->ctrl_reg);  in roclk_recalc_rate()
374 	v = readl(refo->ctrl_reg + REFO_TRIM_REG);  in roclk_recalc_rate()
457 	err = readl_poll_timeout(refo->ctrl_reg, v, !(v & REFO_ACTIVE),  in roclk_set_parent()
469 	v = readl(refo->ctrl_reg);  in roclk_set_parent()
473 	writel(v, refo->ctrl_reg);  in roclk_set_parent()
497 	err = readl_poll_timeout(refo->ctrl_reg, v,  in roclk_set_rate_and_parent()
506 	v = readl(refo->ctrl_reg);  in roclk_set_rate_and_parent()
520 	writel(v, refo->ctrl_reg);  in roclk_set_rate_and_parent()
523 	v = readl(refo->ctrl_reg + REFO_TRIM_REG);  in roclk_set_rate_and_parent()
526 	writel(v, refo->ctrl_reg + REFO_TRIM_REG);  in roclk_set_rate_and_parent()
529 	writel(REFO_ON | REFO_DIVSW_EN, PIC32_SET(refo->ctrl_reg));  in roclk_set_rate_and_parent()
532 	err = readl_poll_timeout_atomic(refo->ctrl_reg, v, !(v & REFO_DIVSW_EN),  in roclk_set_rate_and_parent()
535 	writel(REFO_ON, PIC32_CLR(refo->ctrl_reg));  in roclk_set_rate_and_parent()
575 	refo->ctrl_reg = data->ctrl_reg + core->iobase;  in pic32_refo_clk_register()
587 	void __iomem *ctrl_reg;  member
657 	v = readl(pll->ctrl_reg);  in spll_clk_recalc_rate()
707 	v = readl(pll->ctrl_reg);  in spll_clk_set_rate()
715 	writel(v, pll->ctrl_reg);  in spll_clk_set_rate()
749 	spll->ctrl_reg = data->ctrl_reg + core->iobase;  in pic32_spll_clk_register()
754 	spll->idiv = (readl(spll->ctrl_reg) >> PLL_IDIV_SHIFT) & PLL_IDIV_MASK;  in pic32_spll_clk_register()