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Searched refs:_REG (Results 1 – 10 of 10) sorted by relevance

/Linux-v4.19/drivers/gpu/drm/meson/
Dmeson_venc.c917 priv->io_base + _REG(VENC_VDAC_SETTING)); in meson_venc_hdmi_mode_set()
919 writel_relaxed(0, priv->io_base + _REG(ENCI_VIDEO_EN)); in meson_venc_hdmi_mode_set()
920 writel_relaxed(0, priv->io_base + _REG(ENCP_VIDEO_EN)); in meson_venc_hdmi_mode_set()
927 writel_relaxed(0x12, priv->io_base + _REG(ENCI_CFILT_CTRL)); in meson_venc_hdmi_mode_set()
928 writel_relaxed(0x12, priv->io_base + _REG(ENCI_CFILT_CTRL2)); in meson_venc_hdmi_mode_set()
931 writel_relaxed(0, priv->io_base + _REG(VENC_DVI_SETTING)); in meson_venc_hdmi_mode_set()
934 writel_relaxed(0, priv->io_base + _REG(ENCI_VIDEO_MODE)); in meson_venc_hdmi_mode_set()
935 writel_relaxed(0, priv->io_base + _REG(ENCI_VIDEO_MODE_ADV)); in meson_venc_hdmi_mode_set()
939 priv->io_base + _REG(ENCI_SYNC_HSO_BEGIN)); in meson_venc_hdmi_mode_set()
941 priv->io_base + _REG(ENCI_SYNC_HSO_END)); in meson_venc_hdmi_mode_set()
[all …]
Dmeson_vpp.c51 writel(mux, priv->io_base + _REG(VPU_VIU_VENC_MUX_CTRL)); in meson_vpp_setup_mux()
66 priv->io_base + _REG(VPP_OSD_SC_CTRL0)); in meson_vpp_setup_interlace_vscaler_osd1()
70 priv->io_base + _REG(VPP_OSD_SCI_WH_M1)); in meson_vpp_setup_interlace_vscaler_osd1()
73 priv->io_base + _REG(VPP_OSD_SCO_H_START_END)); in meson_vpp_setup_interlace_vscaler_osd1()
75 priv->io_base + _REG(VPP_OSD_SCO_V_START_END)); in meson_vpp_setup_interlace_vscaler_osd1()
78 writel_relaxed(BIT(16), priv->io_base + _REG(VPP_OSD_VSC_INI_PHASE)); in meson_vpp_setup_interlace_vscaler_osd1()
79 writel_relaxed(BIT(25), priv->io_base + _REG(VPP_OSD_VSC_PHASE_STEP)); in meson_vpp_setup_interlace_vscaler_osd1()
81 writel_relaxed(0, priv->io_base + _REG(VPP_OSD_HSC_CTRL0)); in meson_vpp_setup_interlace_vscaler_osd1()
90 priv->io_base + _REG(VPP_OSD_VSC_CTRL0)); in meson_vpp_setup_interlace_vscaler_osd1()
95 writel_relaxed(0, priv->io_base + _REG(VPP_OSD_SC_CTRL0)); in meson_vpp_disable_interlace_vscaler_osd1()
[all …]
Dmeson_viu.c101 priv->io_base + _REG(VIU_OSD1_MATRIX_PRE_OFFSET0_1)); in meson_viu_set_osd_matrix()
103 priv->io_base + _REG(VIU_OSD1_MATRIX_PRE_OFFSET2)); in meson_viu_set_osd_matrix()
105 priv->io_base + _REG(VIU_OSD1_MATRIX_COEF00_01)); in meson_viu_set_osd_matrix()
107 priv->io_base + _REG(VIU_OSD1_MATRIX_COEF02_10)); in meson_viu_set_osd_matrix()
109 priv->io_base + _REG(VIU_OSD1_MATRIX_COEF11_12)); in meson_viu_set_osd_matrix()
111 priv->io_base + _REG(VIU_OSD1_MATRIX_COEF20_21)); in meson_viu_set_osd_matrix()
116 _REG(VIU_OSD1_MATRIX_COEF22_30)); in meson_viu_set_osd_matrix()
119 _REG(VIU_OSD1_MATRIX_COEF31_32)); in meson_viu_set_osd_matrix()
122 _REG(VIU_OSD1_MATRIX_COEF40_41)); in meson_viu_set_osd_matrix()
124 _REG(VIU_OSD1_MATRIX_COLMOD_COEF42)); in meson_viu_set_osd_matrix()
[all …]
Dmeson_crtc.c99 priv->io_base + _REG(VPP_POSTBLEND_H_SIZE)); in meson_crtc_atomic_enable()
102 priv->io_base + _REG(VPP_MISC)); in meson_crtc_atomic_enable()
118 priv->io_base + _REG(VPP_MISC)); in meson_crtc_atomic_disable()
169 priv->io_base + _REG(VIU_OSD1_CTRL_STAT)); in meson_crtc_irq()
171 priv->io_base + _REG(VIU_OSD1_BLK0_CFG_W0)); in meson_crtc_irq()
173 priv->io_base + _REG(VIU_OSD1_BLK0_CFG_W1)); in meson_crtc_irq()
175 priv->io_base + _REG(VIU_OSD1_BLK0_CFG_W2)); in meson_crtc_irq()
177 priv->io_base + _REG(VIU_OSD1_BLK0_CFG_W3)); in meson_crtc_irq()
179 priv->io_base + _REG(VIU_OSD1_BLK0_CFG_W4)); in meson_crtc_irq()
203 priv->io_base + _REG(VPP_MISC)); in meson_crtc_irq()
Dmeson_dw_hdmi.c366 readl_relaxed(priv->io_base + _REG(VPU_HDMI_SETTING)); in dw_hdmi_phy_init()
425 writel_relaxed(0, priv->io_base + _REG(ENCI_VIDEO_EN)); in dw_hdmi_phy_init()
427 writel_relaxed(0, priv->io_base + _REG(ENCP_VIDEO_EN)); in dw_hdmi_phy_init()
431 priv->io_base + _REG(VPU_HDMI_SETTING)); in dw_hdmi_phy_init()
433 priv->io_base + _REG(VPU_HDMI_SETTING)); in dw_hdmi_phy_init()
437 writel_relaxed(1, priv->io_base + _REG(ENCI_VIDEO_EN)); in dw_hdmi_phy_init()
439 writel_relaxed(1, priv->io_base + _REG(ENCP_VIDEO_EN)); in dw_hdmi_phy_init()
443 priv->io_base + _REG(VPU_HDMI_SETTING)); in dw_hdmi_phy_init()
448 priv->io_base + _REG(VPU_HDMI_SETTING)); in dw_hdmi_phy_init()
451 priv->io_base + _REG(VPU_HDMI_SETTING)); in dw_hdmi_phy_init()
[all …]
Dmeson_drv.c90 (void)readl_relaxed(priv->io_base + _REG(VENC_INTFLAG)); in meson_irq()
156 writel_relaxed(0x210000, priv->io_base + _REG(VPU_RDARB_MODE_L1C1)); in meson_vpu_init()
157 writel_relaxed(0x10000, priv->io_base + _REG(VPU_RDARB_MODE_L1C2)); in meson_vpu_init()
158 writel_relaxed(0x900000, priv->io_base + _REG(VPU_RDARB_MODE_L2C1)); in meson_vpu_init()
159 writel_relaxed(0x20000, priv->io_base + _REG(VPU_WRARB_MODE_L2C1)); in meson_vpu_init()
Dmeson_plane.c119 priv->io_base + _REG(VIU_OSD1_CTRL_STAT2)); in meson_plane_atomic_update()
126 priv->io_base + _REG(VIU_OSD1_CTRL_STAT2)); in meson_plane_atomic_update()
178 priv->io_base + _REG(VPP_MISC)); in meson_plane_atomic_disable()
Dmeson_venc_cvbs.c180 writel_bits_relaxed(BIT(5), 0, priv->io_base + _REG(VENC_VDAC_DACSEL0)); in meson_venc_cvbs_encoder_enable()
Dmeson_registers.h20 #define _REG(reg) ((reg) << 2) macro
/Linux-v4.19/sound/soc/qcom/
Dlpass-lpaif-reg.h128 LPAIF_RDMA##reg##_REG(v, chan) : \
129 LPAIF_WRDMA##reg##_REG(v, chan)