Searched refs:RD_REG_WORD (Results 1 – 15 of 15) sorted by relevance
29 data = RD_REG_WORD(®->nvram); in qla2x00_lock_nvram_access()32 data = RD_REG_WORD(®->nvram); in qla2x00_lock_nvram_access()37 RD_REG_WORD(®->u.isp2300.host_semaphore); in qla2x00_lock_nvram_access()39 data = RD_REG_WORD(®->u.isp2300.host_semaphore); in qla2x00_lock_nvram_access()44 RD_REG_WORD(®->u.isp2300.host_semaphore); in qla2x00_lock_nvram_access()46 data = RD_REG_WORD(®->u.isp2300.host_semaphore); in qla2x00_lock_nvram_access()62 RD_REG_WORD(®->u.isp2300.host_semaphore); in qla2x00_unlock_nvram_access()77 RD_REG_WORD(®->nvram); /* PCI Posting. */ in qla2x00_nv_write()81 RD_REG_WORD(®->nvram); /* PCI Posting. */ in qla2x00_nv_write()84 RD_REG_WORD(®->nvram); /* PCI Posting. */ in qla2x00_nv_write()[all …]
159 mb0 = RD_REG_WORD(®->mailbox0); in qla27xx_dump_mpi_ram()160 RD_REG_WORD(®->mailbox1); in qla27xx_dump_mpi_ram()237 mb0 = RD_REG_WORD(®->mailbox0); in qla24xx_dump_ram()357 for (cnt = 10000; RD_REG_WORD(®->mailbox0) != 0 && in qla24xx_soft_reset()420 RD_REG_WORD(®->hccr); in qla2xxx_dump_ram()430 RD_REG_WORD(®->hccr); in qla2xxx_dump_ram()436 RD_REG_WORD(®->hccr); in qla2xxx_dump_ram()461 *buf++ = htons(RD_REG_WORD(dmp_reg)); in qla2xxx_read_window()760 fw->hccr = htons(RD_REG_WORD(®->hccr)); in qla2300_fw_dump()766 (RD_REG_WORD(®->hccr) & HCCR_RISC_PAUSE) == 0 && in qla2300_fw_dump()[all …]
62 hccr = RD_REG_WORD(®->hccr); in qla2100_intr_handler()75 RD_REG_WORD(®->hccr); in qla2100_intr_handler()80 } else if ((RD_REG_WORD(®->istatus) & ISR_RISC_INT) == 0) in qla2100_intr_handler()83 if (RD_REG_WORD(®->semaphore) & BIT_0) { in qla2100_intr_handler()85 RD_REG_WORD(®->hccr); in qla2100_intr_handler()105 RD_REG_WORD(®->semaphore); in qla2100_intr_handler()110 RD_REG_WORD(®->hccr); in qla2100_intr_handler()189 hccr = RD_REG_WORD(®->hccr); in qla2300_intr_handler()206 RD_REG_WORD(®->hccr); in qla2300_intr_handler()294 ha->mailbox_out[cnt] = RD_REG_WORD(wptr); in qla2x00_mbx_completion()[all …]
49 first = RD_REG_WORD(addr); in qla2x00_debounce_register()52 second = RD_REG_WORD(addr); in qla2x00_debounce_register()
2279 ha->pci_attr = RD_REG_WORD(®->ctrl_status); in qla2100_pci_config()2323 if ((RD_REG_WORD(®->hccr) & HCCR_RISC_PAUSE) != 0) in qla2300_pci_config()2331 RD_REG_WORD(®->ctrl_status); in qla2300_pci_config()2341 RD_REG_WORD(®->ctrl_status); in qla2300_pci_config()2346 if ((RD_REG_WORD(®->hccr) & HCCR_RISC_PAUSE) == 0) in qla2300_pci_config()2361 ha->pci_attr = RD_REG_WORD(®->ctrl_status); in qla2300_pci_config()2511 if ((RD_REG_WORD(®->hccr) & in qla2x00_reset_chip()2517 RD_REG_WORD(®->hccr); /* PCI Posting. */ in qla2x00_reset_chip()2523 RD_REG_WORD(®->ctrl_status); /* PCI Posting. */ in qla2x00_reset_chip()2527 RD_REG_WORD(®->fpm_diag_config); /* PCI Posting. */ in qla2x00_reset_chip()[all …]
2002 ha->mailbox_out[cnt] = RD_REG_WORD(wptr); in qla82xx_mbx_completion()2077 mb[1] = RD_REG_WORD(®->mailbox_out[1]); in qla82xx_intr_handler()2078 mb[2] = RD_REG_WORD(®->mailbox_out[2]); in qla82xx_intr_handler()2079 mb[3] = RD_REG_WORD(®->mailbox_out[3]); in qla82xx_intr_handler()2146 mb[1] = RD_REG_WORD(®->mailbox_out[1]); in qla82xx_msix_default()2147 mb[2] = RD_REG_WORD(®->mailbox_out[2]); in qla82xx_msix_default()2148 mb[3] = RD_REG_WORD(®->mailbox_out[3]); in qla82xx_msix_default()2241 mb[1] = RD_REG_WORD(®->mailbox_out[1]); in qla82xx_poll()2242 mb[2] = RD_REG_WORD(®->mailbox_out[2]); in qla82xx_poll()2243 mb[3] = RD_REG_WORD(®->mailbox_out[3]); in qla82xx_poll()
2850 ha->aenmb[1] = RD_REG_WORD(®->aenmailbox1); in qlafx00_async_event()2851 ha->aenmb[2] = RD_REG_WORD(®->aenmailbox2); in qlafx00_async_event()2852 ha->aenmb[3] = RD_REG_WORD(®->aenmailbox3); in qlafx00_async_event()2853 ha->aenmb[4] = RD_REG_WORD(®->aenmailbox4); in qlafx00_async_event()2854 ha->aenmb[5] = RD_REG_WORD(®->aenmailbox5); in qlafx00_async_event()2855 ha->aenmb[6] = RD_REG_WORD(®->aenmailbox6); in qlafx00_async_event()2856 ha->aenmb[7] = RD_REG_WORD(®->aenmailbox7); in qlafx00_async_event()2943 mb[0] = RD_REG_WORD(®->mailbox16); in qlafx00_intr_handler()2949 ha->aenmb[0] = RD_REG_WORD(®->aenmailbox0); in qlafx00_intr_handler()
404 mb[0] = RD_REG_WORD(®->isp24.mailbox0); in qla2x00_mailbox_command()405 mb[1] = RD_REG_WORD(®->isp24.mailbox1); in qla2x00_mailbox_command()406 mb[2] = RD_REG_WORD(®->isp24.mailbox2); in qla2x00_mailbox_command()407 mb[3] = RD_REG_WORD(®->isp24.mailbox3); in qla2x00_mailbox_command()408 mb[7] = RD_REG_WORD(®->isp24.mailbox7); in qla2x00_mailbox_command()421 ictrl = RD_REG_WORD(®->isp.ictrl); in qla2x00_mailbox_command()566 RD_REG_WORD(®->isp.ctrl_status), in qla2x00_mailbox_command()567 RD_REG_WORD(®->isp.ictrl), in qla2x00_mailbox_command()568 RD_REG_WORD(®->isp.istatus)); in qla2x00_mailbox_command()5201 mb0 = RD_REG_WORD(®->mailbox0); in qla81xx_write_mpi_register()
3965 mb[1] = RD_REG_WORD(®->mailbox_out[1]); in qla8044_intr_handler()3966 mb[2] = RD_REG_WORD(®->mailbox_out[2]); in qla8044_intr_handler()3967 mb[3] = RD_REG_WORD(®->mailbox_out[3]); in qla8044_intr_handler()
114 #define RD_REG_WORD(addr) readw(addr) macro845 RD_REG_WORD(MAILBOX_REG(ha, reg, num))854 RD_REG_WORD(FB_CMD_REG(ha, reg))
156 value = RD_REG_WORD(window); in qla27xx_read16()
1885 RD_REG_WORD(®->ictrl); in qla2x00_enable_intrs()1900 RD_REG_WORD(®->ictrl); in qla2x00_disable_intrs()
767 ha->mailbox_out[0] = RD_REG_WORD(®->mailbox0); in qla1280_mailbox_timeout()770 RD_REG_WORD(®->ictrl), RD_REG_WORD(®->istatus)); in qla1280_mailbox_timeout()868 RD_REG_WORD(&ha->iobase->istatus)); in qla1280_error_action()871 RD_REG_WORD(&ha->iobase->host_cmd), in qla1280_error_action()872 RD_REG_WORD(&ha->iobase->ictrl), jiffies); in qla1280_error_action()1091 RD_REG_WORD(&ha->iobase->ictrl); /* PCI Posted Write flush */ in qla1280_disable_intrs()1099 RD_REG_WORD(&ha->iobase->ictrl); /* PCI Posted Write flush */ in qla1280_enable_intrs()1470 RD_REG_WORD(®->host_cmd); in qla1280_initialize_adapter()1619 data = RD_REG_WORD(®->ictrl); in qla1280_chip_diag()1635 RD_REG_WORD(®->id_l); /* Flush PCI write */ in qla1280_chip_diag()[all …]
60 #define RD_REG_WORD(addr) readw_relaxed(addr) macro64 #define RD_REG_WORD(addr) inw((unsigned long)addr) macro65 #define RD_REG_WORD_dmasync(addr) RD_REG_WORD(addr)
102 RD_REG_WORD(®->ictrl);
