Searched refs:EXYNOS_DOUT_AUD_BUS (Results 1 – 8 of 8) sorted by relevance
16 #define EXYNOS_DOUT_AUD_BUS 3 macro
43 <&clock_audss EXYNOS_DOUT_AUD_BUS>,
36 <&clock_audss EXYNOS_DOUT_AUD_BUS>,
138 <&clock_audss EXYNOS_DOUT_AUD_BUS>;
148 <&clock_audss EXYNOS_DOUT_AUD_BUS>,
104 <&clock_audss EXYNOS_DOUT_AUD_BUS>;
75 <&clock_audss EXYNOS_DOUT_AUD_BUS>,
210 clk_table[EXYNOS_DOUT_AUD_BUS] = clk_hw_register_divider(dev, in exynos_audss_clk_probe()