Searched +full:zynqmp +full:- +full:ddrc +full:- +full:2 (Results 1 – 3 of 3) sorted by relevance
1 # SPDX-License-Identifier: GPL-2.0-only3 ---4 $id: http://devicetree.org/schemas/memory-controllers/synopsys,ddrc-ecc.yaml#5 $schema: http://devicetree.org/meta-schemas/core.yaml#10 - Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>11 - Manish Narani <manish.narani@xilinx.com>12 - Michal Simek <michal.simek@xilinx.com>15 The ZynqMP DDR ECC controller has an optional ECC support in 64-bit and16 32-bit bus width configurations.18 The Zynq DDR ECC controller has an optional ECC support in half-bus width[all …]
1 // SPDX-License-Identifier: GPL-2.0+3 * dts file for Xilinx ZynqMP5 * (C) Copyright 2014 - 2019, Xilinx, Inc.11 * published by the Free Software Foundation; either version 2 of15 #include <dt-bindings/dma/xlnx-zynqmp-dpdma.h>16 #include <dt-bindings/power/xlnx-zynqmp-power.h>17 #include <dt-bindings/reset/xlnx-zynqmp-resets.h>20 compatible = "xlnx,zynqmp";21 #address-cells = <2>;22 #size-cells = <2>;[all …]
5 * Copyright (C) 2012 - 2014 Xilinx, Inc.9 * the Free Software Foundation, either version 2 of the License, or68 #define CTRL_BW_SHIFT 2105 /* ZynqMP Enhanced DDR memory controller registers that are relevant to ECC */151 #define ECC_CTRL_CLR_CE_ERRCNT BIT(2)155 #define DDRCTL_EWDTH_16 2202 /* DDRC Software control register */205 /* DDRC ECC CE & UE poison mask */209 /* DDRC Device config masks */220 #define DDR_MAX_BANKGRP_SHIFT 2[all …]
