Lines Matching +full:zynqmp +full:- +full:ddrc +full:- +full:2
1 # SPDX-License-Identifier: GPL-2.0-only
3 ---
4 $id: http://devicetree.org/schemas/memory-controllers/synopsys,ddrc-ecc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
11 - Manish Narani <manish.narani@xilinx.com>
12 - Michal Simek <michal.simek@xilinx.com>
15 The ZynqMP DDR ECC controller has an optional ECC support in 64-bit and
16 32-bit bus width configurations.
18 The Zynq DDR ECC controller has an optional ECC support in half-bus width
19 (16-bit) configuration.
27 - xlnx,zynq-ddrc-a05
28 - xlnx,zynqmp-ddrc-2.40a
37 - compatible
38 - reg
41 - if:
45 const: xlnx,zynqmp-ddrc-2.40a
48 - interrupts
56 - |
57 memory-controller@f8006000 {
58 compatible = "xlnx,zynq-ddrc-a05";
62 - |
64 #address-cells = <2>;
65 #size-cells = <2>;
67 memory-controller@fd070000 {
68 compatible = "xlnx,zynqmp-ddrc-2.40a";
70 interrupt-parent = <&gic>;